System level design space exploration for multiprocessor system on chip

Future embedded systems will integrate hundreds of pro-cessors. Current design space exploration methods cannot cope with such a complexity. It is mandatory to extend these methods in order to meet future design constraints. We be-lieve one solution is to add a new design exploration step above current methods. This extension corresponds to an abstraction rising to provide designer with a restricted de-sign space. We propose in this work to enrich the classical exploration approaches by a pre-exploration step which re-duces the architecture design space. This new step i) simpli-fies ii) performs and iii) makes possible, for a complex ap-plication the architecture exploration for future tera-scale multiprocessor-based systems. This method drastically re-duces the architecture space at a higher level of the design flow which mitigates the codesign complexity and enables the designer to explore a large set of architectures.