DESIGNERS PURSUING HIGHER PERFORMANCE

have raised SoC clock frequencies to several gigahertz, revealing many challenging issues in global clock distrib-ution and synchronization. Another recent approach to high SoC performance, besides raising clock frequencies, involves the adoption of multiple processing cores to exploit parallelism. The second-generation Itanium 2 microprocessor, for example, has two cores. The first-gen-eration Cell processor combines eight streaming proces-sors to provide high-performance computing for multimedia and streaming workloads.1 One mobile-appli-cation SoC has three ARM9 processor cores and one DSP core integrated for low power consumption while provid-ing high-performance multimedia functionalities.2 Clearly, this trend will persist and accelerate, and the number of cores integrated on a single chip will keep increasing.