A Hardware/Software Approach for Alleviating Scalability Bottlenecks in Transactional Memory Applications

ii ACKNOWLEDGEMENTS There are almost too many people to thank that have helped me survive my trials through the PhD program here at the University of Michigan. I would first like to thank my advisor Professor Trevor Mudge who took a chance tak-ing me on as a student in the Fall of 2005 and providing funding when I was still unsure if I could survive in the program. His hands off advising style was a perfect fit that al-lowed me to pursue what I found interesting, but still hands on enough to help me ask the right questions about what I was doing to continue making progress toward eventually graduating. Thanks to Taeho Kgil, a senior graduate student I used as my surrogate advisor when Trevor was on sabbatical my first year. His patience in answering my endless stream of questions about all things regarding research and the state-of-the-art in computer architec-ture was invaluable in pointing me towards finding my niche. I would like to thank Ronald Dreslinski for spending numerous hours editing papers with me