Harvard University

The unpredictable nature of modern workloads, characterized by frequent branches and control transfers, can result in processor pipeline utilization as low as 19%. Chip multithreading (CMT), a processor architecture combining chip multiprocessing and hardware multithreading, is designed to address this issue. Hardware vendors plan to ship CMT systems within the next year, so now is the time for us to understand how to get the most performance out of these systems. In this work we demonstrate how to leverage operating system scheduling to improve performance on CMT systems, and keep them performing well even when contention for shared resources is high. We have studied several of the most-contended shared resources in CMT systems in order to understand how contention for these resources affects overall system performance. Having analyzed the processor pipeline, L1 data cache and L2 cache, we have found that contention for the processor pipeline is not likely to be an issue for typical workloads, poor hit rate in the L1 does not have a signification impact on overall throughput, but sub-optimal performance in the L2 does have a potential to noticeably hurt performance. To produce good L2 performance, we have used a scheduling policy based on the balance-set principle. With this approach, we are able to reduce miss rates in the L2 by 20-40 % and improve system throughput by 16-32%. To achieve a similar improvement in hardware the size of the L2 cache would have to be quadrupled