An FPGA architecture with enhanced datapath functionality

Although FPGAs are a cost-efcient alternative for both ASICs and general purpose processors, they still result in designs which are more than an order of magnitude more costly and slower than their equivalents implemented in dedicated logic. This efciency gap makes FPGAs less suitable for high-volume cost-sensitive applica-tions (e.g. embedded systems). We show that the intrinsic cost of traditional general-purpose FP-GAs can be reduced if they are designed to target an application domain or a class of applications only. We propose a method of the application-domain characterization and apply it to characterize DSP. A novel FPGA logic block architecture derived based on such an analysis, and which exploits properties of target applications, is presented. Its key feature is the 'mixed-level granularity ' being a trade-off between ne and coarse granularity required for the im-plementation of datapath and random logic functions, respectively. This leads to a factor of four improvement in the LUT memory size compared to commercial FPGAs, and, assuming a standard-cell implementation, a 1.6-2.8 lower datapath mapping cost. A modied mixed-grain architecture with the ALU-like functional-ity reduces the LUT memory size by a factor of 16 compared to commercial FPGAs, and mapped onto standard cells has a 1.9-3.3 times higher datapath mapping efciency. For these reasons, the proposed FPGA architectures may be an interesting alternative to the traditional general-purpose FPGA devices, especially if charac-teristics of a target application domain are known a priori