Formal verification of behavior of a component application requires a suitable specification language. It is necessary that the specification language captures all important aspects of the future implementation with respect to desired properties. Behavior Protocols have been proven to be a suitable component behavior specification platform if one is interested in absence of communication errors. In this thesis, we (1) propose a new specification language based on Behavior Protocols and (2) address the issue of insufficient performance of BPChecker-a proprietary tool for verification of absence of communication errors in Behavior Protocols. Motivated by issues raised during specification of a real-life-sized case study aiming at providing wi...
Growth of the computability power in the last years enabled practical use of model checking of softw...
The component based development is a well established methodology of software development. The indus...
A typical problem formal verification faces is the size of the model of a system being verified. Eve...
Formal verification of behavior of a component application requires a suitable specification languag...
Using software components is a modern approach for building extensible and reliable applications. To...
Behavior protocol is a formalism used for behavior specification of software components. In a regula...
Behavior protocol is a formalism used for behavior specification of software components. In a regula...
Using behavior protocol for behavior specification of components in hierarchical components model (S...
In order to formally verify a component application, it is suitable to structure the formal specific...
Errors such as deadlock and race conditions are very common yet extremely difficult to debug in the ...
Errors such as deadlock and race condition are very common yet extremely difficult to debug in the c...
Growth of the computability power in the last years enabled practical use of model checking of softw...
Growth of the computability power in the last years enabled practical use of model checking of softw...
Growth of the computability power in the last years enabled practical use of model checking of softw...
The component based development is a well established methodology of software development. The indus...
Growth of the computability power in the last years enabled practical use of model checking of softw...
The component based development is a well established methodology of software development. The indus...
A typical problem formal verification faces is the size of the model of a system being verified. Eve...
Formal verification of behavior of a component application requires a suitable specification languag...
Using software components is a modern approach for building extensible and reliable applications. To...
Behavior protocol is a formalism used for behavior specification of software components. In a regula...
Behavior protocol is a formalism used for behavior specification of software components. In a regula...
Using behavior protocol for behavior specification of components in hierarchical components model (S...
In order to formally verify a component application, it is suitable to structure the formal specific...
Errors such as deadlock and race conditions are very common yet extremely difficult to debug in the ...
Errors such as deadlock and race condition are very common yet extremely difficult to debug in the c...
Growth of the computability power in the last years enabled practical use of model checking of softw...
Growth of the computability power in the last years enabled practical use of model checking of softw...
Growth of the computability power in the last years enabled practical use of model checking of softw...
The component based development is a well established methodology of software development. The indus...
Growth of the computability power in the last years enabled practical use of model checking of softw...
The component based development is a well established methodology of software development. The indus...
A typical problem formal verification faces is the size of the model of a system being verified. Eve...