LDPC binary vectors coding enhances transmissions and memories reliability

The paper interests in the research and implementation of memory coded information by modulation with highly effective concatenated codes, represented by LDPC (Low Density Parity Check) codes. Parameters optimization of coding is solved with respect to its implementation by semicustom integrated circuit of gate array and highly effective ARM processor created as SoC (System on Chip). Vendors offer a lot of types programmable circuits and software environments for this technique now. Basic modelling technique is model creation and simulation special architectures described by modeling in C/C++, and SystemC languages. The basic idea – the instruction set extension of the ARM processor – is realized by freely programmable gates as special “data flow” controlled execution unit and additional instruction decoder. © Springer International Publishing AG 2017.Cebia - Tech Research Centre of Czech Republic [CZ.1.05/2.1.00/03.0089