Multi-path ageing sensor for cost-efficient delay fault prediction

Aggressive technology scaling has accelerated the susceptibility of CMOS devices to aging effects. Consequently, the speed of a path can degrade significantly over time; this results in delay faults. Dynamic reliability management schemes have been proposed to ensure an IC's lifetime reliability. Such schemes are typically based on the use of aging sensors to predict a circuit's failure before errors actually appear. Existing aging sensors are usually placed on the circuit's longest delay paths, which are deemed to be the most vulnerable to delay faults. However, complex designs typically have a large number of long delay paths that need to be monitored. Such approaches are very costly and may be infeasible. This work proposes a new aging sensor, capable of monitoring multiple paths concurrently. The proposed sensor has been designed at transistor level using a 32nm technology and applied to a 32-bit MIPS to monitor 10 paths concurrently. Our results show that using the proposed sensor for monitoring 10 paths can save 197.1% and 97.1% in area overheads compared to Razor and Canary, respectively