CPU power estimation using PMCs and its application in gem5

Fast and accurate estimation of CPU power consumption is necessary to inform run-time power management approaches and allow effective design space exploration. Power simulators, combined with a full-system architectural simulator such as gem5, enable power-performance trade-offs to be investigated early in the design of a system. However, the accuracy of existing power simulators is known to be low, and this can lead to incorrect conclusions being made. In this talk, I will present our statistically rigorous methodology for building accurate run-time power models using Performance Monitoring Counters (PMCs) for mobile and embedded devices, and demonstrate how our models make more efficient use of limited training data and better adapt to unseen scenarios by uniquely considering stability. Models built using the methodology for both ARM Cortex-A7 and Cortex-A15 CPUs exhibit a 3.8% and 2.8% average error respectively. I will also present online resources that we have made available from the work, including software tools, documentation, raw data and further results. I will also present results from an investigation into the correlation between gem5 activity statistics and hardware PMCs. Based on this, a gem5 power model for a simulated quadcore ARM Cortex-A15 has been created, built using the above methodology, and its accuracy compared against experimental results obtained from hardware