Examining the relationship between capacitance-voltage hysteresis and accumulation frequency dispersion in InGaAs metal-oxide-semiconductor structures based on the response to post-metal annealing

In this work, we investigated the effect of forming gas annealing (FGA, 5% H2/95% N2, 250 °C to 450 °C) on border trap density in high-k/InGaAs metal-oxide-semiconductor (MOS) systems using accumulation frequency dispersion and capacitance-voltage (CV) hysteresis analysis. It is demonstrated that the optimum FGA temperature that reduces the accumulation frequency dispersion is 350 °C for HfO2/n-InGaAs and 450 °C for Al2O3/n-InGaAs MOS system. Volume density of border traps (Nbt) is estimated using the accumulation frequency dispersion based on a distributed model for border traps. It is shown that for HfO2/n-InGaAs MOS system, Nbt is reduced from 9.4 × 1019 cm− 3 eV− 1 before FGA to 6.3 × 1019 cm− 3 eV− 1 following FGA at 350 °C. For the case of Al2O3/n-InGaAs MOS system, Nbt is reduced from 5.7 × 1019 cm− 3 eV− 1 for no FGA to 3.4 × 1019 cm− 3 eV− 1 for FGA at 450 °C. Furthermore, it is shown that the most pronounced reduction in border trap density estimated from CV hysteresis analysis is observed at the same optimum FGA temperature that reduces the accumulation frequency dispersion, indicating that these two techniques for border trap analysis are correlated