Electron velocity decline in Si nanoscale MOSFETs with the shortening of gate length

The ensemble Monte Carlo device simulations are employed to obtain I-V characteristics for the 25 nm gate length template Si MOSFETs designed by the SiNANO consortium. The simulated ID-VG characteristics are compared against previous results from various Monte Carlo device codes [Fiegna C et al., in Proc. SISPAD 2007, pp. 57-60 (Springer Vienna, 2007)]. After this verification, we have scaled the transistor laterally only from a gate length of 25 nm to gate lengths of 20, 15, 10 and 5 nm. We have then monitored the average electron velocity and sheet density along the channel at a supply voltage of 1.0 V in order to gain an insight into the degradation of the injection velocity experimentally observed in various Si transistor architectures when the gate length is scaled into deep sub-50 nm dimensions. We have found a substantial decrease of the overall velocity profile along the channel including a decrease of the peak velocity when the channel is smaller than 15 nm while the drive current is able to sustain its increase thanks to the increasing velocity at the drain side