Development and characterisation of a radiation hard readout chip for the LHCb experiment

Within this doctoral thesis parts of the radiation hard readout chip Beetle have been developed and characterised, before and after irradiation. The design work included the analogue memory with the corresponding readout amplifier as well as components of the digital control circuitry. An interface compatible with the I2C-standard and the control logic for event readout have been implemented. A scheme has been developed which ensures the robustness of the Beetle chip against Single-Event Upset (SEU). This includes the consistent use of triple-redundant memory devices together with a self-triggered correction in parts of the circuit. The Beetle ASIC is a 128 channel pipelined readout chip for silicon strip detectors. The front-end consists of a charge-sensitive preamplifier and a CR-RC pulse shaper. It features an equivalent noise charge of ENC = 497 e− +48.3 e−/pF·Cin. The analogue memory is a switched capacitor array, which provides a latency of max. 4 µs. The 128 channels are transmitted off chip in 900 ns via a current driver. Beside the pipelined readout path, the Beetle provides a fast discrimination of the front-end pulse. A total ionising dose irradiation of Beetle1.1 up to 45 Mrad showed no functional failure and only slight degradation in the analogue performance. Chip version 1.2 fulfils the requirements of the vertex detector (VELO), the inner tracker (ITR) and the RICH detectors of the LHCb experiment