Radiation Tolerant Design with 0.18-micron CMOS Technology

This thesis discusse s th e issues r elated to the us e of enclosed-gate layou t trans isto rs and guard rings in a 0.18 μ m CMOS technology in order to im prove the radiation tolerance of ASICs. The thin gate oxides of subm icron technologies ar e inherently m ore radiation tole rant tha n the thick er oxides present in less advanced technologies. Using a commercial deep subm icron technology to bu ild up radiation-ha rdened circuits introduces several advantages com pared to a dedicated radiation-ha rd technology, such as speed, power, area, stability, and expense. Som e novel aspects related to the use of encl osed-gate layout transist ors are presented in this th esis. A m odel to calculate the aspect ratio is introduced and verified. Some im portant electrica l par ameters of the tran sistors such as threshold voltage, leakage current, subthreshold slope, and transconducta nce are studied before and after being irradiation up to 70 kGy(SiO 2 ). Th e analy zed electrical p aram eters shift a very lim ited am ount a fter the irradiation. This research shows that a 0.18 μ m CM OS t echnology (gate oxide thickness of 4.3 nm ), com bined with enclosed-gate layout tr ansistors and guard rings can effectively resis t total dose e ffe cts to a very high level (m ore than 70 kGy(SiO 2 )) with negligible perform ance degradation. A digital library is develope d with enclosed-gate layout tr ansistors and a configurable SRAM architecture is introduced. Som e lo w-power techniques are adopted, such as divided-word line structure, automatic pow er down function, and address transition detection. A SRAM test chip is designed and fabricated with the custom -designed library. Single-event upsets becom e m ore s ignificant in deep submicron techn ologies than the less advanced ones which have a larger feat ure size, because of the decreas ed charg e needed to flip the state of a node in a circ uit. There are m any techniques for hardening the SRAM to guard agains t single-ev ent upset. These hardening techniques are introduced and evaluated with the 0.18 μ m te chnology. An overall best solution is determ ined in term s of power, speed, and area