The Timing and Fast Control Demonstrator

In this thesis, the feasibility of an FPGA to host a system for generating and distributing clocks as well as distributing synchronous and asynchronous commands is tested. This system will be an imitation of the SHiP (Search for Hidden Particle) DAQ (Data Acquisition) system led by CERN. The practical implementation is to mainly apply Altera Cyclone V GT development board attached with SFP+ daughter card to achieve accurate timing and high speed performance. Experiments include three loopback test implementations. Loopback test is the simplest technique to assess a channel’s integration. The first one is the Ethernet loopback test. An Ethernet card daughter board is inserted to the HSMC port of the Cyclone V GT development board. After that, a SFP card is applied alternatively on the same port to do the similar loopback test but at a much higher speed via optical fibers. And finally, a more advanced XAUI to SFP+ card daughter board will be used to replace the previous SFP card in order to get a further speed improvement at around 10Gbps. The last part is being implemented to check whether the system can distribute clock and data even on higher transfer rates. An alternative, more appropriate, DE4 FPGA development board is also used for the last experiment part apart from Cyclone V. The system is implemented by Altera Cyclone V GT board, Altera DE4 board, Terasic Ethernet-HSMC board, Terasic SFP-HSMC card and Dual XAUI to SFP+ HSMC card. The design is built and programmed by the Quartus II 13.1 and Nios II Software Build Tool. Some embedded tools of Quartus for test and verification are used including Transceiver Toolkit and SignalTap II Logic Analyzer