Differential Phase Detector for Precise Phase Alignment

This paper presents a differential phase detector circuit, whose phase-to-voltage characteristic has an extremum when its two input signals are exactly in phase. In this condition all its digital signals are of 50 % duty cycle so that the circuit characteristic does not have a dead zone. This feature allows a precise indication of the zero-phase condition, which is independent of the detector power supply and the offset of its ADC readout. Such a detector is used for a phase alignment of two reference clock signals with frequency about 11 kHz in front-ends processing signals from beam position monitors of the Large Hadron Collider (LHC) at CERN. The detector output voltage is digitized with a 24-bit ADC at the rate of the reference signals. The resulting samples are processed in the front-end FPGA and transmitted to the control system using an Ethernet data stream. After a detailed description of the differential phase detector its performance is demonstrated with laboratory measurements. The results show that this simple circuit allows a phase alignment resolution of the 11.2 kHz clock signals in the order of 0.0001 º with a measurement bandwidth of 1 Hz