We report on the design of a serializer ASIC to be used in the ATLAS forward muon detector for trigger data transmission. We discuss the performance of a prototype chip covering power dissipation, latency and stable operating line rate. Tests show that the serializer is capable of running at least at 5.76 Gbps with a bit error ratio below 1x10^{-15}, and a power consumption of 200 mW running at 4.8 Gbps. The latency between the start of loading 30 bits into the serializer to the transmission of the first bit from the serializer is measured to be about 6 ns
Based on a commercially available 0.25 µm Silicon on Sapphire CMOS technology, we are developing the...
The upgrades of the LHC accelerator and the experiments in 2019/20 and 2023/24 will increase the ins...
This paper presents the design and simulation results of a gigabit transceiver Application Specific ...
The small-strip Thin-Gap Chambers (sTGC) will be used as both trigger and precision tracking muon de...
A small-strip thin gap chamber (sTGC) will be used for both triggering and precision tracking purpos...
The small-strip Thin-Gap Chambers (sTGC) will be used as both trigger and precision tracking muon de...
The upgrade of the ATLAS muon spectrometer for the high-luminosity LHC requires new trigger and read...
The ATLAS Muon Spectrometer endcap thin-Resistive Plate Chamber trigger project compliments the New ...
The High Performance Time to Digital Converter (HPTDC), a multi-channel ASIC designed by the CERN Mi...
The current front-end electronics of the ATLAS Liquid Argon calorimeters need to be upgraded to sust...
A prototype TDC LSI for the ATLAS precision muon tracker (MDT) has been developed. The LSI was proce...
An ASIC has been fabricated in order to readout data from an MWPC that is installed in high rate env...
A new TDC LSI (AMT-2) for the ATLAS Muon detector has been developed. The AMT-2 chip is a successor ...
The ART Data Driver Card (ADDC) will be used in the ATLAS muon upgrade to process and transmit the A...
A high speed 16:1 serializer ASIC has been developed using a commercial 0.25 μm silicon-on-sapphire ...
Based on a commercially available 0.25 µm Silicon on Sapphire CMOS technology, we are developing the...
The upgrades of the LHC accelerator and the experiments in 2019/20 and 2023/24 will increase the ins...
This paper presents the design and simulation results of a gigabit transceiver Application Specific ...
The small-strip Thin-Gap Chambers (sTGC) will be used as both trigger and precision tracking muon de...
A small-strip thin gap chamber (sTGC) will be used for both triggering and precision tracking purpos...
The small-strip Thin-Gap Chambers (sTGC) will be used as both trigger and precision tracking muon de...
The upgrade of the ATLAS muon spectrometer for the high-luminosity LHC requires new trigger and read...
The ATLAS Muon Spectrometer endcap thin-Resistive Plate Chamber trigger project compliments the New ...
The High Performance Time to Digital Converter (HPTDC), a multi-channel ASIC designed by the CERN Mi...
The current front-end electronics of the ATLAS Liquid Argon calorimeters need to be upgraded to sust...
A prototype TDC LSI for the ATLAS precision muon tracker (MDT) has been developed. The LSI was proce...
An ASIC has been fabricated in order to readout data from an MWPC that is installed in high rate env...
A new TDC LSI (AMT-2) for the ATLAS Muon detector has been developed. The AMT-2 chip is a successor ...
The ART Data Driver Card (ADDC) will be used in the ATLAS muon upgrade to process and transmit the A...
A high speed 16:1 serializer ASIC has been developed using a commercial 0.25 μm silicon-on-sapphire ...
Based on a commercially available 0.25 µm Silicon on Sapphire CMOS technology, we are developing the...
The upgrades of the LHC accelerator and the experiments in 2019/20 and 2023/24 will increase the ins...
This paper presents the design and simulation results of a gigabit transceiver Application Specific ...