Fabrication and performance of 50 nm T-gates for InP high electron mobility transistors

Fifty nanometre gate length T-gates In<sub>0.52</sub>A1<sub>0.48</sub>As/In<sub>0.53</sub>Ga<sub>0.47</sub>As high electron mobility transistors (HEMTs) on a InP substrate were fabricated with high resolution electron-beam (e-beam) lithography using a novel UVIII/LOR/PMMA T-gate resist stack and with a non-selective digital wet etch gate recess technology. The reproducibility of the gate lithography depends on the substrate slope when mounted on the holder of e-beam lithography tool. This mounting effect is almost eliminated by calibrating the tool using a specially fabricated marker on the wafer instead of the holder marker as in usual. Initial devices exhibited a maximum transconductance (<i>g</i><sub>m</sub>) of 950 mS/mm and a current cut-off frequency (<i>f</i><sub>t</sub>) of 300 GHz