In this thesis we show the feasibility of Coarse Grained Data Flow Machines for high-throughput streaming non-manifest applications. The architecture of the Coarse Grained Data Flow Machine is derived from the classical data flow architecture and the scheduling of its processing elements is done dynamically in hardware. Since the implementation of such an architecture is strongly application dependent, a design flow and supporting software tools, are provided. This gives application designers the means by which the number of processing elements, buffer sizes and latencies of the architecture can be tuned
This chapter addresses reconfigurable heterogenous and homogeneous multicore system-on-chip (SoC) pl...
The synchronous dataflow (SDF) model has proven efficient for represent-ing an important class of di...
The present paper describes an approach to the design of application-oriented software for Digital S...
Data driven streaming applications are quite common in modern multimedia and wireless applications, ...
This paper concerns automatic hardware synthesis from data flow graph (DFG) specification for fast H...
This paper reviews a set of techniques for compiling dataflow-based, graphical programs for embedded...
Coarse-grain reconfigurable arrays often rely on an imperative programming approach including a read...
International audienceDomain-specific acceleration is now a "must" for all the computing spectrum, g...
Domain-specific acceleration is now a “must” for all the computing spectrum, going from high perform...
The potential computational power of today multicore processors has drastically improved compared to...
In application areas that process stream-like data such as multimedia, networking and DSP, the pipel...
Abstract- This paper concerns area-efficient automatic hardware architecture synthesis and its optim...
Emerging applications such as high definition television (HDTV), streaming video, image processing i...
Abstract in Undetermined This paper describes a methodology for the optimization of portable paralle...
PhD ThesisEmerging applications such as high definition television (HDTV), streaming video, image pr...
This chapter addresses reconfigurable heterogenous and homogeneous multicore system-on-chip (SoC) pl...
The synchronous dataflow (SDF) model has proven efficient for represent-ing an important class of di...
The present paper describes an approach to the design of application-oriented software for Digital S...
Data driven streaming applications are quite common in modern multimedia and wireless applications, ...
This paper concerns automatic hardware synthesis from data flow graph (DFG) specification for fast H...
This paper reviews a set of techniques for compiling dataflow-based, graphical programs for embedded...
Coarse-grain reconfigurable arrays often rely on an imperative programming approach including a read...
International audienceDomain-specific acceleration is now a "must" for all the computing spectrum, g...
Domain-specific acceleration is now a “must” for all the computing spectrum, going from high perform...
The potential computational power of today multicore processors has drastically improved compared to...
In application areas that process stream-like data such as multimedia, networking and DSP, the pipel...
Abstract- This paper concerns area-efficient automatic hardware architecture synthesis and its optim...
Emerging applications such as high definition television (HDTV), streaming video, image processing i...
Abstract in Undetermined This paper describes a methodology for the optimization of portable paralle...
PhD ThesisEmerging applications such as high definition television (HDTV), streaming video, image pr...
This chapter addresses reconfigurable heterogenous and homogeneous multicore system-on-chip (SoC) pl...
The synchronous dataflow (SDF) model has proven efficient for represent-ing an important class of di...
The present paper describes an approach to the design of application-oriented software for Digital S...