New scan-based test strategy for a dependable many-core processor using a NoC as a Test Access Mechanism

Periodic on-chip scan-based tests have to be applied to a many-core processor to improve its dependability. This paper describes an infrastructural IP module that has been designed and incorporated into an SoC to function as an ATE. The Network-on-Chip inside the SoC is reused as a test access mechanism. Since the scan-based test is performed on-chip via the NoC during functional execution, it needs to share the NoC bandwidth with other applications. Instead of reserving sufficient NoC bandwidth for the test, the authors propose a novel way to carry out scan-based tests by dynamically pausing and resuming the test data flow to accommodate the fluctuating communication bandwidth available on the NoC. A Test Pattern Generator and Test Response Evaluator with pause functionality and special test wrappers around the processor cores have been designed for this purpose. The system and the IIP have been implemented in synthesizable VHDL. Simulation results prove the correct application of standard manufacturing test patterns to processor cores at run-time, using the pause/resume functionality and the NoC. Silicon of this system is expected at the end of 2010