A Noise Tolerant and Low Power Dynamic Logic Circuit Using Finfet Technology

For the improvement of performance and noise tolerance in dynamic logic circuits, a technique is\ud proposed in this paper. A two-input AND gate is designed and simulated in 32nm technology using FinFET\ud device. Simulation results indicate that the proposed technique provides improvement in noise tolerance of\ud about three times and the use of FinFET device reduces the power consumption over the conventional MOSFET\ud designs