Transmission Lines in CMOS: An Explorative Study

On-chip transmission line modelling and design become increasingly important as frequencies are continuously going up. This paper explores possibilities to implement transmission lines on CMOS ICs via coupled coplanar strips. EM-field simulations with SONNET are used to estimate important transmission line properties like characteristic impedance, propagation velocity and loss in a 0.18 micron CMOS Technology. Both metal losses and substrate losses are modeled. Special attention is paid to the effect of the Silicon substrate, in particular to the so called “slow-wave mode‿ that can occur in the Si-SiO2 system