Add to ORKGGlobal on-chip communication is rapidly becoming a speed and power bottleneck in CMOS circuits. In this paper, a ‘mixed-signal’ approach is taken to analyze on-chip interconnects and it is investigated how data-rates can be improved. It is shown that complex signaling schemes such as OFDM and CDMA are not efficient to improve the data-rate, while equalization can significantly improve the achievable data-rate. A combination of an equalizing transmitter with a low-ohmic receiver can improve the achievable data-rate by about a factor of 7
102 p.Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 2006.We mitigate the effects of in...
This thesis tackles the problem of high-speed data communication over wireline channels. Particular...
The performance of many digital systems today is limited by the interconnection bandwidth between ch...
Global on-chip data communication is becoming a concern as the gap between transistor speed and inte...
The data rate of global on-chip interconnects (up to 10 mm) is limited by a large distributed resist...
In the earlier days of the Complementary Metal Oxide Semiconductor (CMOS) industry, much effort was ...
Abstract—Global on-chip data communication is becoming a concern as the gap between transistor speed...
Abstract—Global on-chip data communication is becoming a concern as the gap between transistor speed...
Global on-chip communication is receiving quite some attention as global interconnects are rapidly b...
As technology scales, interconnect planning has been widely regarded as one of the most critical fac...
With the rapid increase in transmission speeds of communication systems, the demand for very high-sp...
As semiconductor technology advances in the ultra deep sub -micron era, on-chip global interconnecti...
schemes have been proposed to mitigate the performance degrada-tion caused by the scaling of on-chip...
Abstract—Global on-chip data communication is becoming a concern as the gap between transistor speed...
This thesis work explores the use of equalization techniques to improve throughput and reduce power ...
102 p.Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 2006.We mitigate the effects of in...
This thesis tackles the problem of high-speed data communication over wireline channels. Particular...
The performance of many digital systems today is limited by the interconnection bandwidth between ch...
Global on-chip data communication is becoming a concern as the gap between transistor speed and inte...
The data rate of global on-chip interconnects (up to 10 mm) is limited by a large distributed resist...
In the earlier days of the Complementary Metal Oxide Semiconductor (CMOS) industry, much effort was ...
Abstract—Global on-chip data communication is becoming a concern as the gap between transistor speed...
Abstract—Global on-chip data communication is becoming a concern as the gap between transistor speed...
Global on-chip communication is receiving quite some attention as global interconnects are rapidly b...
As technology scales, interconnect planning has been widely regarded as one of the most critical fac...
With the rapid increase in transmission speeds of communication systems, the demand for very high-sp...
As semiconductor technology advances in the ultra deep sub -micron era, on-chip global interconnecti...
schemes have been proposed to mitigate the performance degrada-tion caused by the scaling of on-chip...
Abstract—Global on-chip data communication is becoming a concern as the gap between transistor speed...
This thesis work explores the use of equalization techniques to improve throughput and reduce power ...
102 p.Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 2006.We mitigate the effects of in...
This thesis tackles the problem of high-speed data communication over wireline channels. Particular...
The performance of many digital systems today is limited by the interconnection bandwidth between ch...