This paper proposes an efficient implementation of the H.264/AVC motion estimation algorithm in hardware and software. Furthermore, a complete codesign trajectory from the HW/SW partitioning to the actual implementation on two different targets is shown. A Leon 3 + FPGA and an ARM + Montium implementation have been successfully realized. The FPGA implementation shows a speed-up of 43.6 whereas the Montium implementation shows a speedup of 21.5, both compared to a software-only implementation. Power consumption is 42.0 mW for the FPGA and 60.2 mW for the Montium. A co-simulation tool, CosiMate, is used to achieve both on target implementations in just five weeks
International audienceImage and video processing applications represent major challenge concerning r...
This paper presents a high-performance hardware architecture for the H.264/AVC Half-Pixel Motion Est...
International audienceBlock matching motion estimation is the heart of video coding system. It leads...
This paper proposes an efficient implementation of the H.264/AVC motion estimation algorithm in hard...
Abstract High resolution video (720p, 1080i and 1080p frame sizes, up to 60 fps), even if widespr...
Abstract The paper presents a hardware friendly fast algorithm and its architecture for motion estim...
[[abstract]]We propose a hardware accelerator for H.264/AVC motion compensation. Our design supports...
Multiview video coding (MVC) is the process of efficiently compressing stereo (two views) or multivi...
Abstract- In order to increase transmission efficiency of the real world video sequences, Motion est...
In this paper, we investigate the use of Field-Programmable Gate Arrays (FPGAs) in the design of a h...
H.264/AVC is the latest standard for video compression and is a significant advance, but at the expe...
In this paper, we present a high performance and low cost hardware architecture for real-time implem...
AbstractThe H.264/AVC is the Standard Video Format used by the SBTVD (Sistema Brasileiro de Televisã...
In this paper, we propose a Graphics Processing Unit (GPU)-based motion estimation for H.264/AVC by ...
Les architectures mixtes contenant des composants programmables et d'autres reconfigurables peuvent ...
International audienceImage and video processing applications represent major challenge concerning r...
This paper presents a high-performance hardware architecture for the H.264/AVC Half-Pixel Motion Est...
International audienceBlock matching motion estimation is the heart of video coding system. It leads...
This paper proposes an efficient implementation of the H.264/AVC motion estimation algorithm in hard...
Abstract High resolution video (720p, 1080i and 1080p frame sizes, up to 60 fps), even if widespr...
Abstract The paper presents a hardware friendly fast algorithm and its architecture for motion estim...
[[abstract]]We propose a hardware accelerator for H.264/AVC motion compensation. Our design supports...
Multiview video coding (MVC) is the process of efficiently compressing stereo (two views) or multivi...
Abstract- In order to increase transmission efficiency of the real world video sequences, Motion est...
In this paper, we investigate the use of Field-Programmable Gate Arrays (FPGAs) in the design of a h...
H.264/AVC is the latest standard for video compression and is a significant advance, but at the expe...
In this paper, we present a high performance and low cost hardware architecture for real-time implem...
AbstractThe H.264/AVC is the Standard Video Format used by the SBTVD (Sistema Brasileiro de Televisã...
In this paper, we propose a Graphics Processing Unit (GPU)-based motion estimation for H.264/AVC by ...
Les architectures mixtes contenant des composants programmables et d'autres reconfigurables peuvent ...
International audienceImage and video processing applications represent major challenge concerning r...
This paper presents a high-performance hardware architecture for the H.264/AVC Half-Pixel Motion Est...
International audienceBlock matching motion estimation is the heart of video coding system. It leads...