Advances in silicon phased-array receiver IC's

Abstract - Phased-Arrays are increasingly used, and require Silicon implementations to result in affordable multi-beam systems. In this paper, CMOS implementations of two novel analogue beamforming multi-channel receivers will be presented. A narrow-band highly linear system exploiting switches and capacitors in advanced CMOS is presented, implementing a fully passive switched capacitor vector modulator exploiting a zero-IF I/Q mixer. This technique is not applicable to very wideband phased-array receivers. These systems require true-time delay beamforming, which is implemented in the second CMOS implementation. An innovative gm-RC implementation of a truetime delay cell is exploited in a four-channel beamforming receiver with more than 1.5 GHz bandwidth, in a standard 0.13 urn CMOS process. Professional phased-arrays can often not live with the dynamic range limitations imposed by these implementations. To that end a SiGe implementation of an integrated receiver was realized targeting a digital beamforming phased-array. Dynamic range and flexibility of use were the main driving factors. Alltogether, these results show large progress with respect to the feasibility of Silicon-based phased-array frontend implementation for commercial as well as professional phased-arrays