A power efficient 2Gb/s transceiver in 90nm CMOS for 10mm On-Chip interconnect

Abstract—Global on-chip data communication is becoming a concern as the gap between transistor speed and interconnect bandwidth increases with CMOS process scaling. In this paper a low-swing transceiver for 10mm long 0.54μm wide on-chip interconnect is presented, which achieves a similar data rate as previous designs (a few Gb/s), but at much lower power than recently published work. Both low static power and low dynamic power (low energy per bit) is aimed for. A capacitive pre-emphasis transmitter lowers the voltage swing and increases the bandwidth using a simple inverter based transceiver and capacitive coupling to the interconnect. The receiver uses Decision Feedback Equalization with a power-efficient continuous-time feedback filter. A low power latch-type voltage sense amplifier is used. The transceiver, fabricated in a 1.2V 90nm CMOS process, achieves 2Gb/s. It consumes only 0.28pJ/b, which is 7 times lower than earlier work