A reconfigurable function array architecture for 3G and 4G wireless terminals

Advance in low-power hand-held multimedia systems requires exploration of novel system architectures. In conventional computer architectures, an increase in processing power also implies an increase in energy consumption. In a mobile system this results in a shorter operating-time. Limiting the generality of an architecture can improve its energy efficiency. However, application specific architectures have a number of drawbacks and are too restricted. Therefore, an application domain specific architecture is proposed. As part of an application domain specific architecture for the digital signal-processing domain, the Field Programmable Function Array (FPFA) was conceived. The FPFA is a reconfigurable device with a data-path that can be configured to implement a number of DSP algorithms energy efficiently. The flexibility in the FPFA results in a data-path that requires many control signals. To reduce the vast amount of control signals, the FPFA control-path uses a combination of configuration registers and vertical microprogramming