Design citeria for apllications with non-manifest loops

In the design process of high-throughput applications, design choices concerning the type of processor architecture and appropriate scheduling mechanism, have to be made. Take a reed-solomon decoder as an example, the amount of clock cycles consumed in decoding a code is dependent on the amount of errors within that code. Since this is not known in advance, and the environment in which the code is transmitted can cause a variable amount of errors within that code, a processor architecture which employs a static scheduling scheme, has to assume the worst case amount of clock cycles in order to cope with the worst case situation and provide correct results. On the other hand a processor that employs a dynamic scheduling scheme, can gain wasted clock cycles, by scheduling the exact amount of clock cycles that are needed and not the amount of clock cycles needed for the worst case situation. Since processor architectures that employ dynamic scheduling schemes have more overhead, designers have to make their choice beforehand. In this paper we address the problem of making the correct choice of whether to use a static or dynamic scheduling scheme. The strategy is to determine whether the application possess non-manifest behavior and weigh out this dynamic behavior against static scheduling solutions which were quite common in the past. We provide criteria for choosing the correct scheduling architecture for a high throughput application based upon the environmental and algorithm-specification constraints. Keywords¿ Non-manifest loop scheduling, variable latency functional units, dynamic hardware scheduling, self scheduling hardware units, optimized data-flow machine architecture