On the reduction of the third order distortion in a CMOS triode transconductor

This paper presents a linearisation technique which aims to cancel out the third order distortion of a CMOS triode transconductor due to the mobility reduction effect of the conversion transistors. The transconductor consist of a parallel operating voltage and current biased differential pair. It is realised in a 0.8 ¿m CMOS process. Simulation results, obtained with state-of-the-art MOS models, show a significant deviation from the measurement results. It is shown that the third order distortion prediction of the generally used `&thetas;-model' for mobility reduction is rather poor in the triode regio