An Efficient Fault Tolerance System Design for Cmos/Nanodevice Digital Memories

Targeting on the future fault-prone hybrid CMOS/Nanodevice digital memories, this paper present two faulttolerance\ud design approaches the integrally address the tolerance for defect and transient faults. These two\ud approaches share several key features, including the use of a group of Bose-Chaudhuri- Hocquenghem (BCH)\ud codes for both defect tolerance and transient fault tolerance, and integration of BCH code selection and dynamic\ud logical-to-physical address mapping. Thus, a new model of BCH decoder is proposed to reduce the area and\ud simplify the computational scheduling of both syndrome and chien search blocks without parallelism leading to\ud high throughput.The goal of fault tolerant computing is improve the dependability of systems where\ud dependability can be defined as the ability of a system to deliver service at an acceptable level of confidence in\ud either presence or absence falult.ss The results of the simulation and implementation using Xilinx ISE software\ud and the LCD screen on the FPGA’s Board will be shown at last