This paper describes a design-for-testability expert system for the selection of the most appropriate test method for every macro within an IC. The interface with the system designer is user-friendly and together with an efficient search mechanism this expert system can be used as a framework for all types of macros. This tool will be used in a self-test compiler, which generates the layout of self-testable macros automatically. The self-test compiler can be part of a silicon compilation system and thus contribute to the integration of testability into the design proces
The Programmable Logic Array (PLA) macro is a physical structure which simpl8es LSZ chip design whil...
An increasing part of the overall costs of custom and semicustom integrated circuits has to be spent...
International audienceThe principles of SYCO are explained and its characteristics compared with tho...
Describes CASTOR (Computer Aided System Testability OptimizeR), which is able to support CAD designe...
At Philips Research Laboratories a silicon compiler for digital signal processor applications has be...
The IC production process contains uncertainties by nature. Therefore, every IC should undergo a str...
Silicon compilation is a term used for many different purposes. In this paper we define silicon comp...
In the past, research has shown that the use of high-level test knowledge can be used to greatly acc...
This paper presents a Computer Aided Testability tool named STA (System Testability Assistant), aimi...
TIES is a knowledge based system that advises the ICs designer on the best modifications to perform ...
This chapter describes and analyzes a methodology for gathering together test-programs for microproc...
This thesis presents a new approach to building a design for testability (DFT) system. The system ...
The paper addresses the issue of microprocessor and microcontroller testing, and follows an approach...
Includes bibliographical references (page 91)This project presents a Microprocessor System for Autom...
The era of VLSI design necessitates the development of advanced Computer Aided Design tools. The mai...
The Programmable Logic Array (PLA) macro is a physical structure which simpl8es LSZ chip design whil...
An increasing part of the overall costs of custom and semicustom integrated circuits has to be spent...
International audienceThe principles of SYCO are explained and its characteristics compared with tho...
Describes CASTOR (Computer Aided System Testability OptimizeR), which is able to support CAD designe...
At Philips Research Laboratories a silicon compiler for digital signal processor applications has be...
The IC production process contains uncertainties by nature. Therefore, every IC should undergo a str...
Silicon compilation is a term used for many different purposes. In this paper we define silicon comp...
In the past, research has shown that the use of high-level test knowledge can be used to greatly acc...
This paper presents a Computer Aided Testability tool named STA (System Testability Assistant), aimi...
TIES is a knowledge based system that advises the ICs designer on the best modifications to perform ...
This chapter describes and analyzes a methodology for gathering together test-programs for microproc...
This thesis presents a new approach to building a design for testability (DFT) system. The system ...
The paper addresses the issue of microprocessor and microcontroller testing, and follows an approach...
Includes bibliographical references (page 91)This project presents a Microprocessor System for Autom...
The era of VLSI design necessitates the development of advanced Computer Aided Design tools. The mai...
The Programmable Logic Array (PLA) macro is a physical structure which simpl8es LSZ chip design whil...
An increasing part of the overall costs of custom and semicustom integrated circuits has to be spent...
International audienceThe principles of SYCO are explained and its characteristics compared with tho...