Ultra low voltage and low power Static Random Access Memory design using average 6.5T technique

Power Stringent Static Random Access Memory (SRAM) design is very much essential in embedded systems such as biomedical implants, automotive electronics and energy harvesting devices in which battery life, input power and execution delay are of main concern. With reduced supply voltage, SRAM cell design will go through severe stability issues. In this paper, we present a highly stable average nT SRAM cell for ultra-low power in 125nm technology. The distinct difference between the proposed technique and other conventional methods is about the data independent leakage in the read bit line which is achieved by newly introduced block mask transistors. An average 6.5T SRAM and average 8T SRAM are designed and compared with 6T SRAM, 8T SRAM, 9T SRAM, 10T SRAM and 14T SRAM cells. The result indicates that there is an appreciable decrease in power consumption and delay