Analysis and Comparison of CMOS Comparator At 90 NM Technology

In this paper, A CMOS comparator with low power dissipation is presented. The preamplifier latch comparator\ud is compared with conventional double tail comparator. The comparators designed and simulated in 90nm\ud Cadence virtuoso environment technology. The particular preamplifier latch comparator will be mix of a good\ud amplifier and a latch comparator can easily effect higher velocity and also low electric power dissipation. The\ud proposed circuit topology improves kickback noise and reduces power dissipation compared with a conventional\ud double tail comparator.Analysis are testified and compared with conventional comparator and enhancements\ud are detected in this paper