Realizing Ternary Logic in FPGAs for SWL DSP Systems

Recently SWL (Short Word Length) DSP (Digital Signal Processing) applications has been proposed to overcome multiplier complexity that is evident in most of the digital applications. These SWL applications have been processed through sigma-delta modulation as a key element. For such applications, adder design plays vital role and can impact upon the chip area and its performance. In this paper, a ternary approach for adder tree has been proposed instead of binary that can accommodate more data with less chip-area at the cost of extra pin. The proposed ternary adder tree has been designed and developed in Quartus-II using three different design strategies namely T-gate (Ternary gate), LUT (Look Up Table) and algebraic equations. Through rigorous simulation it was found that T-gate technique results in superior performance, an average of 23.5 and 33% improvement compared to the same adder structure based on Boolean Algebraic Equation and LUT, respectively. The proposed adder design would benefit the efficient implementation of SWL applications