Study of impact of LATID on HCI reliability for LDMOS devices

This paper demonstrates electrical degradation due to Hot Carrier Injection (HCI) stress for nLDMOS devices with different Large Angle Tilted Implantation Doping (LATID) techniques for p-body. It seems that optimization of the device with LATID angle for p-body in nLDMOS is important to achieve improved HCI performance and observed that HCI degradation is minimum for 300 LATID for p-body. We observed Si/SiO2 interface trap under various stress conditions, were evaluation based on our Sentaurus simulation, and we compare trapped charge density and distribution for various LATID angles and it was less for 300 tilt. Trap-related models were employed to perform Ron and Id,sat degradations during the HCI stress test. So nLDMOS device with 300 tilt angle for p-body shows better HCI performance compared to other LATID. Also our new proposed device structure shows less HCI degradations when compared with silicon data of HCI degradations for other nLDMOS structure