Verilog Based Design and Simulation of MAC and PHY Layers for Zigbee Digital Transmitter

The past several years have witnessed a rapid development in the wireless network area. So far wireless\ud networking has been focused on high-speed and long range applications. Zigbee technology was developed for a\ud Wireless Personal Area Networks (WPAN), aimed at control and military applications with low data rate and\ud low power consumption. Zigbee is a standard defines the set of communication protocols for low-data-rate\ud short-range wireless networking. Zigbee-based wireless devices operate in 868 MHz, 915 MHz, and 2.4 GHz\ud frequency bands. The maximum data rate is 250K bits per second. Zigbee is mainly for battery-powered\ud applications where low data rate, low cost, and long battery life are main requirements. This paper explores\ud Verilog design for various blocks in Zigbee Transmitter architecture for an acknowledgement frame. The word\ud digital has made a dramatic impact on our society. Developments of digital solutions have been possible due to\ud good digital system design and modeling techniques. Further developments have been made and introduced\ud VLSI in order to reduce size of the architecture, to improve speed of operation, improvements in predictability\ud of the circuit behavior. Digital Zigbee Transmitter comprises of Cyclic Redundancy Check, Bit-to-Symbol\ud block, Symbol-to-chip block, Modulator and Pulse shaping block. The work here is to show how we can design\ud Zigbee transmitter with its specifications by using Verilog with less number of slices and Look up tables\ud (LUTs)