Design of Low Power Sequential System Using Multi Bit FLIPFLOP With Data Driven Clock Gating

Power reduction plays a vital role in VLSI design .The Data driven clock gating is used for reduce power\ud consumption in synchronous circuits .Common clock gating is used for power saving. However clock gating\ud still leaves larger amount of redundant clock pulses. Multibit flip-flop is also used to reduce power\ud consumption .Using of Multibit Flip-Flop method is to eliminate the total inverter number by sharing the\ud inverters in the flip-flop .Combination of Multibit Flip-Flop with Data driven clock gating will increase the\ud further power saving. Xilinx software tool and quatrus II for power analysis is used for implementing this\ud proposed system.\u