Modified quadrant-based routing algorithm for 3D Torus Network-on-Chip architecture

Due to high performance demands of the consumer electronics and processing systems, like servers, the number of cores is increasing on System-on-Chip (SoC). Network-on-Chip (NoC) is suitable approach for reducing the communication bottleneck of multicore System-on-Chip. With the integration of 3D IC technology, the 3D Network-on-Chip design enhances the execution rate and decreases power utilisation by replacing long flat interconnects with short vertical ones. New compact architectures are possible by arranging the cores in three-dimensions. Optimised routing algorithms can provide higher execution speed along with reduced energy consumption. In this paper an efficient routing algorithm for 3D Torus topology architecture is proposed. A modified quadrant-based routing algorithm for 3D torus NoC architecture is proposed which is primarily based on division of space into different quadrants and also adopting a path which encounters least hops to connect to the destination node. The proposed algorithm is compared with other 3D routing algorithms like XYZ dimension order routing and the simulated results shows that the proposed algorithm has least latency