Design Of High Performance CMOS Dynamic Latch Comparator

High performance analog to digital converters (ADC), memory sense amplifiers, and Radio Frequency identification applications, data receivers with less area and power efficient designs has attracted a broad range of dynamic comparators. This paper presents an ameliorate design for a dynamic latch based comparator in attaining high performance. The comparators accuracyis mainly defined by two factors they are speed and power consumption. The latch based comparator has two different stages encompassing of a dynamic differential input gain stage and an output latch.The output node in the differential gain stage of proposed comparator requires lesser time to regain higher charge potential. The proposed comparator hasbeen designed and simulated using 130nm CMOS 1P2M technology by using mentor graphics tools with a supply voltage of 1V. Proposed dynamic latch comparator iscompared with existing conventional dynamic latch comparator and with other comparators and the results are discussed in detail