A NOVEL DESIGN OF MULTIPLEXER BASED FULL-ADDER CELL FOR POWER AND PROPAGATION DELAY OPTIMIZATIONS

This paper presents a novel high-speed and high-performance multiplexer based full adder cell for low-power applications. The proposed full adder is composed of two separate modules with identical hardware configurations that generate Sum and Carry signals in a parallel manner. The proposed adder circuit has an advantage in terms of short critical path when compared with various existing previous designs. Comprehensive experiments were performed in various situations to evaluate the performance of the proposed design. Simulations were performed by Microwind 2 VLSI CAD tool for LVS and BSIM 4 for parametric analysis of various feature sizes. The simulation results demonstrate clearly the improvement of the proposed design in terms of lower power dissipation, less propagation delay, less occupying area and low power delay product (PDP) compared to other widely used existing full adder circuits