An all-digital on-chip delay sensor (OCDS) circuit with high delay-measurement resolution and low supply-voltage sensitivity for efficient detection and diagnosis in high-performance electronic system applications is presented. Based on the proposed delay measurement scheme, the quantization resolution of the proposed OCDS can be reduced to several picoseconds. Additionally, the proposed cascade-stage delay measurement circuit can enhance immunity to supply-voltage variations of the delay measurement resolution without extra self-biasing or calibration circuits. Simulation results show that the delay measurement resolution can be improved to 1.2 ps; the average delay resolution variation is 0.55% with supply-voltage variations of ±10%. Mor...
This paper presents a delay measurement techniques using signature analysis, and a scan design for t...
A novel calibration technique and its all-digital implementation for the open-loop delay line is pre...
As technology continues to shrink, the challenges of developing manufacturing tests for integrated c...
An all-digital on-chip delay sensor (OCDS) circuit with high delay-measurement resolution and low su...
High-resolution and all-digital on-chip delay measurement with low supply sensitivity for SoC applic...
With the scaling of CMOS technology, critical paths in digital circuits have become largely sensitiv...
This paper proposes a design of voltage sensor with new controllable delay element (CDE) having high...
Abstract—A novel integrated approach for delay-fault testing in external (automatic-test-equipment-b...
Development of high-performance CMOS delay lines is becoming a crucial necessity for many advanced a...
Delay-fault monitoring sensors are widely used for Dynamic Voltage and Frequency Scaling (DVFS) to c...
Thesis: M. Eng., Massachusetts Institute of Technology, Department of Electrical Engineering and Com...
A review on CMOS delay lines with a focus on the most frequently used techniques for high-resolution...
Precise measurement of digital circuit degradation is a key aspect of aging tolerant digital circuit...
This paper proposes an method for testing a circuit in order to improve defect coverage of delays du...
This paper presents a delay measurement technique using signature analysis, and a scan design for th...
This paper presents a delay measurement techniques using signature analysis, and a scan design for t...
A novel calibration technique and its all-digital implementation for the open-loop delay line is pre...
As technology continues to shrink, the challenges of developing manufacturing tests for integrated c...
An all-digital on-chip delay sensor (OCDS) circuit with high delay-measurement resolution and low su...
High-resolution and all-digital on-chip delay measurement with low supply sensitivity for SoC applic...
With the scaling of CMOS technology, critical paths in digital circuits have become largely sensitiv...
This paper proposes a design of voltage sensor with new controllable delay element (CDE) having high...
Abstract—A novel integrated approach for delay-fault testing in external (automatic-test-equipment-b...
Development of high-performance CMOS delay lines is becoming a crucial necessity for many advanced a...
Delay-fault monitoring sensors are widely used for Dynamic Voltage and Frequency Scaling (DVFS) to c...
Thesis: M. Eng., Massachusetts Institute of Technology, Department of Electrical Engineering and Com...
A review on CMOS delay lines with a focus on the most frequently used techniques for high-resolution...
Precise measurement of digital circuit degradation is a key aspect of aging tolerant digital circuit...
This paper proposes an method for testing a circuit in order to improve defect coverage of delays du...
This paper presents a delay measurement technique using signature analysis, and a scan design for th...
This paper presents a delay measurement techniques using signature analysis, and a scan design for t...
A novel calibration technique and its all-digital implementation for the open-loop delay line is pre...
As technology continues to shrink, the challenges of developing manufacturing tests for integrated c...