Towards a Toolchain for Assertion-Driven Test Sequence Generation

International audienceCoverage is a major concern in simulation-based test and verification, but it usually addresses statements, conditions, or FSM transitions. The work reported here focuses on dynamic Assertion-Based Verification, which aims at checking that designs obey requirements formalized as temporal assertions. In that context, the selection of test sequences is related to coverage of the assertions activation conditions. This goal also differs from the one of usual ATPG methods (Automatic Test Pattern Generation), which target the production of test patterns designed to detect incorrect circuit behaviors and that are guided by fault models such as stuck-at faults.This paper describes a toolchain for the automatic construction of test sequence generators directed by specifications expressed as temporal assertions. It also sketches some experimental results and discusses some issues related to the diversity of alternative solutions