A collision management structure for NoC deployment on multi-FPGA

International audienceto integrate ecient communication structures such as Network-on-Chip. Multi-FPGA platforms are considered tobe the most appropriate experimental way to emulate and evaluate these large System-on-Chips. The deploymentoften goes through the Network-on-Chip partitioning on all FPGAs requiring the use of inter-FPGA communicationlinks between routers. The number of external links and their performance restrict the communication bandwidth.Currently, the number of inter-FPGA signals is considered to be a major problem in the Network-on-Chip deployedon multi-FPGAs. As there are more signals to be connected than IOs, inter-FPGA links must be shared betweenrouters leading to significant bottlenecks. As the ratio of the logic capacity to the number of IOs rises slowly for eachFPGA generation, this technological bottleneck will be remaining for future system designs.In this paper, we propose a novel architecture for inter-FPGA collision management in the Network-on-Chippartitioned on multi-FPGAs. The structure ensures to eciently share the external link between several routers witha minimum number of collisions and inter-FPGA bottlenecks. The proposed architecture is easily placed betweenthe Network-on-Chip and the external protocol. The collision management architecture is based on the BackOalgorithm used in Wi-Fi communications and adapted to FPGA platforms. This algorithm balances accesses amongall the routers connected with the inter-board interfacing, thereby avoiding collisions. We compare this structure withtraditional techniques using experimental and theoretical results. The novel inter-FPGA architecture for the Networkon-Chip based on the BackO algorithm achieves lower latency with fewer resources compared to other solutions