Model-driven reliability evaluation for MPSoC design

International audienceWhen designing a Multi-Processor System-on-Chip(MPSoC), a very large range of design alternatives arises froma huge space of possible design options and component choices.Literature proposes numerous Design-Space-Exploration (DSE)approaches which mainly focus on cost optimization. In thispaper, we present a DSE approach which mainly focuses onthe reliability of the whole design. This approach is based ona meta-model of Multi-Processor System-on-Chips (MPSoCs)which integrates the reliability evaluation. We develop a toolthat allows designers to describe and optimize their platformbased on the proposed meta-model. The results obtained for anMPSoC is presented, including the improved overall reliability ofthe system thanks to the automatic selection of the fault tolerancestrategies for each component