Higher switching speed of power devices in series connection achieved by modifying the gate driver architecture

International audienceThis paper presents the study on gate driver circuitries implemented to drive power devices in seriesconnection with the objective to minimize the conducted EMI perturbations and as well to improve theswitching speed of the power devices. More specifically, the propagation paths of parasitic currentsgenerated under very high switching speed are studied in different configurations trying to reduce theparasitic capacitance of each gate driver circuit with respect to ground/control reference potential andto minimize the common mode currents. In complex power converters, multi-cell, multi-level or evenseries connection of power devices, many driver circuits are required and implemented. Similarly, insuch converters, there are several dv/dt sources generated at different floating points that are exitingthe isolated barriers of the gate drivers (supplies and control signal isolation units) which mean thatconducted EMI perturbations can be amplified and the switching speed of the power devices could beaffected by multi-parasitic capacitances. Based on previous works, the paper analyses the best possibleconfigurations to minimize the common mode currents in series connected transistor topologies and toreduce the parasitic capacitance of the gate driver circuitries leading as well to a significant improvementof the switching speed of the power devices. In this article, experimental validations are used to approve the analysis