Improved vertical MOSFET performance using an epitaxial channel and stacked silicon-insulator structure

A vertical MOSFET (VMOST) incorporating an epitaxial channel and a drain junction in a stacked silicon-insulator structure is presented. In this device structure, an oxide layer near the drain junction edge (referred to as a junction stop) acts as a dopant diffusion barrier and consequently a shallow drain junction is formed to suppress short channel effects. To investigate the scalability of this device, a simulation study in the sub-100 nm regime calibrated to measured results on the fabricated devices is carried out. The use of an epitaxial channel delivers 50% higher drive current due to the higher mobility of the retrograde channel and the junction stop structure delivers improvements of threshold voltage roll-off and drain-induced barrier lowering compared with a conventional VMOS