CdTe Solar Cells: Key Layers and Electrical Effects

This thesis presents various studies into the effects of both growth and processing conditions on a) the electrical properties of interfaces of the CdTe solar cell, and b) the photovoltaic (PV) performance. Annealing of the CdS/TCO (transparent conductive oxide) bilayer in both oxidising and reducing ambients was investigated in order to study changes in the electrical properties of the In/CdS/TCO structure. It was found that post-growth oxidising changed the current–voltage (J-V) characteristics from Ohmic to rectifying, which was attributed to the creation of a CdO-n+/CdS-n junction, as an oxygen-rich layer was revealed by Auger electron spectroscopy (AES) on the CdS surface. A new method of testing pinholing of the CdS film was used, which gave confidence that the observed Ohmic behaviour was genuine. Annealing CdS (in various ambients) was further investigated by studying its effect on full devices, but the effect on PV performance was insignificant. This study was paired with an investigation into a rapid screening method of optimising CdTe/CdS cell PV performance, which reduced the number of the required samples by a factor of ~ 30. This was achieved by varying the CdTe thickness by chemically bevelling the cells in a Br2/methanol solution. The best performance was obtained at a CdTe thickness of ~ 3 μm, for which the CdCl2 treatment used was optimum. Both the uniformity and roughness of the cell layers are vital to obtaining high quality results using this methodology. The electrical current transport mechanism in the CdTe/CdS heterojunction was investigated as a function of a) growth technique by which devices were fabricated, and b) window layer type. Data were collected by recording J-V-T measurements in different light intensities (including dark), with temperature being varied in the range of 200 – 300 K. The transport mechanism was found to be dependent only on the window material under forward bias condition in the dark, but was independent of both the window layer and growth technique in a) forward bias in the light, and b) reverse bias in the dark. A new method was used to determine the diode ideality factor in the light, and therefore identify the transport mechanism. The back contact of the CdTe/CdS cell was investigated by measuring its barrier height (b). In a preliminary study, two methods of b measurement were compared, with the most applicable method being used to study Au, Sb2Te3 and As2Te3 contacts, with the CdTe back surface being either a) as-grown, b) nitric/phosphoric acid etched or c) plasma etched. The value of the barrier height for each contact and its impact on the cell performance are presented and discussed