Junctionless nanowire transistors show more marked oscillations conductance oscillations than inversion-mode devices. These oscillations can be observed at higher temperature, drain voltage, and gate voltage than in surface-channel, inversion-mode multigate metal-oxide-semiconductor field-effect devices. Clear oscillations are observed at 77 K at a drain voltage of 100 mV in devices with a 10 x 10 nm(2) cross section. (C) 2010 American Institute of Physics. (doi:10.1063/1.3506899
This paper study the impact of working temperature on the electrical characteristics of gate all ar...
Submitted on behalf of EDA Publishing Association (http://irevues.inist.fr/handle/2042/5920)Internat...
Contains report on one research project.Joint Services Electronics Program (Contract DAAL03-86-K-000...
Negative-bias-temperature-instability (NBTI) and hot-carrier induced device degradation have been ex...
This Letter presents an analysis of the zero temperature coefficient (ZTC) bias in junctionless nano...
The electric field perpendicular to the current flow is found to be significantly lower in junctionl...
The performance of III-V inversion-mode and junctionless nanowire field-effect transistors are inves...
The aim of this work is to analyze the operation of junctionless nanowire transistors down to the li...
The improvement of subthreshold slope due to impact ionization is compared between "standard" invers...
The performance of germanium and silicon inversion-mode and junctionless nanowire field-effect trans...
Single ZnO nanowire (NW) transistors fabricated with self-assembled nanodielectric (SAND) and SiO2 g...
In this work we show that junctionless nanowire transistor (JNT) exhibits lower degree of ballistici...
Metallurgical junction and thermal budget are serious constraints in scaling and performance of conv...
This paper investigates the temperature dependence of the main electrical parameters of junctionless...
Silicon nanowires have numerous potential applications, including transistors, memories, photovoltai...
This paper study the impact of working temperature on the electrical characteristics of gate all ar...
Submitted on behalf of EDA Publishing Association (http://irevues.inist.fr/handle/2042/5920)Internat...
Contains report on one research project.Joint Services Electronics Program (Contract DAAL03-86-K-000...
Negative-bias-temperature-instability (NBTI) and hot-carrier induced device degradation have been ex...
This Letter presents an analysis of the zero temperature coefficient (ZTC) bias in junctionless nano...
The electric field perpendicular to the current flow is found to be significantly lower in junctionl...
The performance of III-V inversion-mode and junctionless nanowire field-effect transistors are inves...
The aim of this work is to analyze the operation of junctionless nanowire transistors down to the li...
The improvement of subthreshold slope due to impact ionization is compared between "standard" invers...
The performance of germanium and silicon inversion-mode and junctionless nanowire field-effect trans...
Single ZnO nanowire (NW) transistors fabricated with self-assembled nanodielectric (SAND) and SiO2 g...
In this work we show that junctionless nanowire transistor (JNT) exhibits lower degree of ballistici...
Metallurgical junction and thermal budget are serious constraints in scaling and performance of conv...
This paper investigates the temperature dependence of the main electrical parameters of junctionless...
Silicon nanowires have numerous potential applications, including transistors, memories, photovoltai...
This paper study the impact of working temperature on the electrical characteristics of gate all ar...
Submitted on behalf of EDA Publishing Association (http://irevues.inist.fr/handle/2042/5920)Internat...
Contains report on one research project.Joint Services Electronics Program (Contract DAAL03-86-K-000...