FINAL REPORT NASA CR-54186 TRW-ER-6586 OPTIMIZATION STUDY OF HIGH POWER STATIC INVERTERS AND CONVERTERS By R. G. Klimo, E. L. Krejny, A. B. Larsen, R. J. Resch, and J. E. Murray of TRW Incorporated Prepared For National Aeronautics and Space Administration September 14, 1964 CONTRACT NAS 3-2785 Technical Management NASA-Lewis Research Center Space Power Systems Division Francis Gourash TRW EQUIPMENT LABORATORIES https://ntrs.nasa.gov/search.jsp?R=19660005464 2020-03-16T21:53:19+00:00Z TABLE OF CONTENTS SUMMARY INTRODUCTION I, INVESTIGATION OF EXISTING INVERTER DESIGNS II. 3200 CPS - I0 KW STATIC INVERTER DESIGN CONSIDERATIONS ILl."400 CPS - 10 KW STATIC INVERTER DESIGN CONSIDERATIONS GENERA L INFORMA TION Io DESCRIPTION OF INVERTER TYPES A. Introductlon B. Parallel Inverter s a. Simple Parallel Inverter b. The McMurray-Bedford Parallel Inverter c. Gate-Controlled Switch Parallel Inverter II. VOLTAGE REGULATION A. Series Proportional DC Regulator B. Series Switching DC Regulator C. Shunt Switching DC Regulator (Bedford Step-Up Circuit) D. Inverter-Rectifier DC Regulators E. Buck-Boost DC Regulators F. Quasi-Square Wave Regulation Techniques a. Quasi-Square Wave Power Stage IlL HARMONIC REDUCTION A. Single Step Waveforms (Quasi-Square Wave) B. Multi-Stepped Outputs C. Constant Voltage Transformer Techniques D. Static Tap Changing 1 6 i0 13 Z5 33 33 33 33 33 35 36 36 37 37 38 39 39 40 4O 4O 4O 41 41 4Z ii TABLE OF CONTENTS (continued) E. High Frequency Techniques F. Passive Filters G. Active Filters 3200 CPS - I0 KW INVERTER DESIGN I. INTRODUCTION Ii STEPPED WAVEFORMS A. Note On Stepped Wave Analysis III. MAGNETIC COMPONENT STUDIES A. Optimum Loading Of A Fixed Transformer B. Scaling Of Transformers C. Relationships Between Size, Weight And Losses D. Multi-Phase Transformers And Circuits Utilizln_ Them E. 3200 CPS Inverter (I0 KW) Power Stage Transformer Analysis a. Transformer Analysis b. Core Material Considerations c. Use of Shunts for Current Limit do Use of Holes in the Iron Core for Current Balancing IV. PARALLELING TECHNIQUES AND PROBLEMS A. The Split Transformer Technique B. Balancing Reactor Techniques a. Reference Balancing Technique b. Closed Chain Balancing Reactors V. GENERAL DESCRIPTION OF PROPOSED 3200 CPS - I0 KW INVERTER DESIGN VI. POWER STAGE A. Final Transformer Design B. Transistor Configuration 42 43 43 45 45 45 50 51 52 54 56 56 61 61 64 67 68 69 69 70 72 74 75 76 76 78 iii TABLE OF CONTENTS (continued) C. AC Filter D. DC Filter E. Weights And Losses VII, LOGIC VIII. Ae B. C. D. E. F. G. Oscillator Ring Counter Phase Shifter Driver Short Circuit Current Limiting Voltage Feedback 200 Watt Voltage Regulator RELIABILITY STUDY AND SCALING FOR 3200 CPS (I0 KW) STATIC INVERTER Ao B. C. Results Of Reliability Stud Y Results Of Class I Scaling Results Of Class II Scaling DESIGN OF A 400 CPS PULSE WIDTH MODULATION INVERTER Pa_e 82 85 86 88 88 89 89 93 95 97 98 99 99 I00 10Z 109 I. INTRODUCTION II. PULSE WIDTH MODULATION A. Classical Pulse Width Modulation a. Uniform Sampling b. Natural Sampling B. Commutated Pulse Width Modulation III. GENERAL DESCRIPTION IV. POWER STAGE A. Power Stage Efficiency B. Power Stage Weight Breakdown 109 109 110 110 112 113 114 115 122 128 iv TABLE OF CONTENTS (continued} Page V. DC-DC CONVERTER STUDY A. Introduction B. Inversion Methods a. Pure Square Wave Generation with External Regulation b. Quasi-Square Wave Generation c. Selection of a System C. Weight And Efficiency Versus Frequency Tradeoffs D. Detailed Design a. Power Stage s b. Rectifier -Filter c. Input Regulator d_ Oscillator and Driver e. Input Filter E. Expected Weights and Losses VI. LOGIC Ao B. C. D. E. F. G. H. I. J. Z. 4 KC Clock Three-Phase Square Wave Oscillator Current Reference Circuit And Attenuators Tuned Amplifiers Sawtooth Sweep Wave Generator Summing Networks Slicer -Amplifier Driver Stages Voltage Regulator Sense Circuit Output Filter VII. TOTAL WEIGHTS AND EFFICIENCIES A. Estimated Weight B. Estimated Efficiency 130 130 130 131 131 132 132 133 133 133 133 134 135 135 136 136 137 138 138 139 140 140 141 142 14Z 143 143 143 V TABLE OF CONTENTS (continued) VIII. RESULTS OF RELIABILITY STUDY FOR 400 CPS - I0 KW PULSE WIDTH MODULATION INVERTER APPENDIX 4-I ANALYSIS OF THE PARALLEL INVERTER A PPENDIX 4-If RELIABILITY STUDY FOR THE 3Z00 CPS - 10 KW STATIC INVERTER A PPENDIX 4-11I SCALING - CLASS I A. Scaling Down In Power Level a. Magnetic Components b. Semiconductor Components c. Logic (Control) Section d. Total Weight and Losses B. Scaling For DC Input Voltage APPENDIX 4-IV PROOF THAT A GROUP OF SCALED TRANSFORMERS FOLLOWS THE SAME WEIGHT VERSUS POWER RATING EQUATION AS A SINGLE TRANSFORMER APPENDIX 4-V SCALING - CLASS II Ae B. C. D. Harmonic Distortion Phase Separation Voltage Regulation DC Variations 144 147 147 158 158 163 163 163 164 165 166 166 166 168 168 169 169 169 17Z 176 180 vi TABLE OF CONTENTS (continued) APPENDIX 4-VI RELIABILITY STUDY FOR THE 400 CPS - I0 KW P. W.M. STATIC INVERTER TABLES FIGURES DISTRIBUTION LIST 184 184 188 199 358 vii SUMMARY The purpose of this study program was to develop high performance static inverter and converter conceptual designs that will fulfill the present and projected requirements for various space applications. High efficiency, high power to weight ratios, and high reliability were the three design goals that were used to optimize these conceptual designs. Since optimizing one or two of these design goals usually degrades the third, a reasonable compromise must be made among the three design goals. The most feasible circuit techniques and advanced circuit components were used to obtain an optimum mix for these three design goals so that high performance static inverter and converter con- ceptual designs can be realized for the various space applications. The power range that was to be examined covered the range of 100 watts to 10,000 watts with operating frequencies of 400 cps to 3200 cps. However, a program redirection was instituted later in this program which directed all efforts toward the development of an optimum design for a 3200 cps - 10 KW inverter and a 400 cps - 10 KW inverter in place of the low and medium power inverter and converter requirements that were originally specified. Certain ground rules and a Methodology Plan were established so that the multitude of performance p_ameters for these inverters and converters could be correlated in order to obtain these optimum conceptual designs. With the basic set of performance specifications for these conceptual designs established, the first phase of this study was directed toward a selection of the most feasible approach for each inverter application. The primary consideration was a selection of the inverter power stage. Therefore, an investigation was conducted on existing designs for both series and parallel inverters so that their operating ranges and their inherent advantages and limitations conld be established. Both these inverter types were designed to use transistors or silicon controlled rectifiers as their switching elements with the series inverters using the silicon controlled rectifiers almost exclusively. The maximum useful load range for the series inverter was limited to approximately 3 to 1. Therefore, no further effort was devoted to these series inverters. The basic parallel inverter designs were investigated next. A typical parallel inverter of the McMurray-Beclford type was analyzed in detail in order to show that it will start and operate under a wide range of load magnitudes and power factors. A detailed mathematical analysis of this parallel inverter is included in the Appendix in order to verify these results and to allow the reader to fully understand the complex sequence of operations which occur in inverter circuits. A general review of various methods of voltage regulation were discussed with the purpose of defining which method of voltage regulation was most suitable for a specific application. Design problems encountered with the different methods of regulation were also included. Various methods of reducing harmonic distortion are outlined in this section in an attempt to determine which method would offer the least circuit complexity and minimum filter weight and size. Two general design approaches were obtained from this preliminary investiga- tion that would satisfy the requirements for high performance static inverters. They were high frequency pulse width modulation techniques and stepped wave techniques. These approaches were considered for the 3200 cps - 10HW inver- ter and 400 cps - 10HW inverter designs. The second section of this report concentrated on the problems of the 3200 cps - 10KW static inverter since its design appeared to be the most difficult and neither of the two design approaches seemed to offer a clear advantage. Many switching devices (silicon and germanium transistors, SCI%'s, and gate controlled switches) were investigated to determine their compatibility when used with either design approach. The results of this investigation revealed that the stepped waveform approach using silicon power transistors would be the most practical means of making a 3200 cps - 10KW inverter. The pulse width moduIation techniques had to be disregarded because switching devices of sufficient current capacity and switching speeds could not be found that would make this approach feasible at this operating frequency of 3200 cps. An analysis was performed on various stepped waveforms in order to obtain a maximum amount of harmonic reduction for a minimum amount of circuit corr_Iexity. The suitability of each waveform for this three-phase inverter was investigated from the standpoint of the number of inverter stages required; the applicability to Delta connections; and the number of different transformers required. The results of this analysis revealed that a twelve step waveforrn requiring six inverters per phase would be an optimum choice. The magnetic components for this 3200 cps - 10KW static inverter approach were considered after the selection of this multi-stepped waveform in order to obtain optimum component designs. The loading characteristics of fixed transformers were considered in order to develop a general set of equations that can be used to scale optimum transformer designs to different power levels without resorting to extensive calculations. In addition_ relationships between the size_ weight_ and loss of both single-phase and multi-phase trans- former designs were established. The analysis of transformer optimization was expanded to include its associated circuitry when the three-phase power output transformers were considered. Flux cancellation was used wherever possible in the design of this multi-phase output transformer in order to minimize its weight and losses. The resulting output transformer design contained twelve windows arranged in two rows of six for use with the twelve- step wavefo rrn. Using this information the design of the 3200 cps - I0 KW power output transformer was detailed. The advautages and disadvantages of various transformer configurations, core materials, use of shunts for current limiting, and use of holes in the transformer core for current balancing were considered. Three optimum output power transformers using Square Permalloy 80, Orthonol, and Supermendur core materials were designed. The rest of the 3200 cps - I0 KW inverter power stages were then considered in detail with emphasis being placed on the transistor switch drive scheme and the AC output filter configuration that will be used. Current feedback was selected to minimize the power transistor base drive losses while a timing core was used in each transistor switch pair to eliminate their "turn on" losses. A total savings of 392 watts was realized with the use of these two schemes. The resulting AC output filter configuration contained a series tank circuit in series with the load and a parallel tank shunting the load. The four filter components were determined so that no harmonic would exceed 2%. A complete theoretical design of the low level logic circuitry was made for this 3200 cps - I0 KW inverter including schematics and parts lists. This completed the detailed theoretical design for this 3200 cps - I0 KW static inverter. Its component weight and overall efficiency were estimated to be 41.5 pounds and 9290 at full load. A reliability study was performed on the electrical circuitry and their parts for the proposed 3200 cps - I0 KW static inverter design• The results of this reliability study could only be used as a guide since this circuitry was created from a theoretical design with no actual stress measurements being taken. These results indicated that this inverter design would have a reliability of • 963506 and . 718930 for one month and one year continuous operation respec- tively. The reliability figures of merit can be improved with the use of redundant circuitry and components that have larger derating factors. The last area of investigation for this static inverter involved scaling its weight, losses, and reliability with respect to reduced power level, DC input voltage, harmonic distortion, output phase separation, voltage regulation, and DC input variations. The effects of scaling this inverter with respect to reduced power level and DC input voltage were of primary interest since a multitude of circuit and component changes will occur. The AC filter compo- nents were effected most by scaling this inverter with respect to harmonic distortion, output phase separation, voltage regulation and DC input variations• No large component changes were observed for this scaling except when separate voltage regulators were required for each phase when the voltage regulation tolerance was reduced below ±2%. The last section of this report was devoted to the design of the 400 cps - 10 KW static inverter. Both the multi-stepped waveform techniques and the pulse width modulation techniques were considered for this inverter design. The information obtained for the selection of the 3200 cps - 10 KW inverter approach was used again as an aid toward selecting the best approach for this 400 cps - 10 KW static inverter. The pulse width modulation scheme was selected for this inverter because an estimated weight savings of 54 pounds could be realized with only a slight sacrifice in efficiency as compared with an equivalent multi-stepped waveform inverter. In addition, the pulse width modulation approach does not require a bulky power output transformer. The elimination of the power output transformer allows the power output stages to be readily adaptable to modular construction. The modular construction tech- niques allow these power output stages to be easily scaled to any power capacity by adding or removing the transistor switch leg modules which are connected in parallel for each half phase. A detailed investigation of the various high frequency pulse width modulation techniques was made to determine which one would produce waveforms with low total harmonic content with relatively simple inverter circuitry. The results of this investigation revealed that classical pulse width modulation with natural sampling required the least amount of circuit complexity and would use a simple and light-weight AC filter. The other pulse width modulation techniques (Classical PWM with uniform sampling, commutated PWM with uniform sampling, and commutated PWM with natural sampling), required either large AC filters with comparable circuit complexity or more complex circuitry with comparable AC filter size and weight. The classical pulse width modulation with natural sampling required a minimum practical carrier frequency of twenty-five times the fundamental or 10 KC so that the frequencies of the carrier and its harmonics and sidebands would be high enough to allow lightweight filter components to be used. Therefore switching components with high voltage, high current, and very fast switching times were required for these output stages. Fast switching times were essential in order to minimize the switching losses that will occur at this 10 KC carrier frequency. Medium power silicon transistors (10 A) with high voltage ratings and extremely fast switching times (_ 2 _s) were available and were found to be the most efficient switching components for these power output stages. Because a minimum safety factor margin of two was used for a design goal, two of these switching transistors must be connected in series to provide an adequate voltage safety margin. In addition, fifteen pairs of these series connected transistors must be connected in parallelfor each half phase in order to supply the necessary capacity for 250% overload conditions. (There are a total of six half-phases that will be used to make up the three phase wye connected output for this inverter). 4 In order to build a transformerless inverter, the input voltage to the power stages must be bi-polar and have sufficient magnitude to produce the required three-phase output voltages. Therefore, a DC-DC converter will usually be required for relatively low voltage sources to step-up the voltage to this desired bi-polar DC voltage level. In addition, this DC-DC converter will be used to regulate the source voltage. A complete theoretical design for the low level logic circuitry, the power stages, and the DC-DC converter was made for this 400 cps - 10 KW static inverter. Both schematics and parts lists were generated from this theoretical design. The overall component weight and efficiency were then determined for this pro- posed conceptual inverter design. Its total component weight was found to be 147. 54 pounds while its total full load efficiency was estimated to be 80.4%. A reliability study was performed on the electrical circuitry and their parts for the proposed 400 cps - 10 KW static inverter design. Again, the results of this reliability study could only be Used as a guide since the stress levels of each electrical component were calculated with no actual stress measure- ments being taken. The same generic failure rates, derating factors, and environmental conditions used for the electrical components for the 3200 cps - 10 KW reliability analysis were used again. A certain amount of redundancy was found in the power output stages depending on its mode of failure and the permissible maximum current allowed. Therefore, the reliability figure of merit for the proposed conceptual inverter design was determined for each of these power stage failure modes. Using a suitable protective device such as fuses in each of the transistor switch legs will eliminate the worst failure mode. (Both switching transistors connected in series for one switch leg that fails in the shorted mode, thus shorting out a half phase and causing possible damage to the DC-DC converter.) The use of redundant circuitry in circuits with the largest failure rates will considerably improve the reliability of this proposed 400 cps - 10 KW static inve rte r. The results of this "Optimization Study of High Power Static Inverters and Converters" has produced two conceptual designs for both 400 cps and 3Z00 cps 10 KW static inverters. A complete set of schematics and parts lists have been generated from these theoretical designs. In addition, reliability, efficiency, and weight have been calculated for these two designs. A more detailed discussion and analysis of these inverter designs is given in the introduction and body of this report. 5 -- II II INTRODUCTION The overall objective of this high power static inverter optimization study program was to develop conceptual designs for efficient, lightweight and highly reliable static power conversion units up to ratings of 10 kilowatts. These inverters would be used for auxiliary electric power systems required for present and future space applications. The considerations which entered the design of these inverters included the performance requirements of the load, the regulation of the DC source, the method of inversion, the environment with its thermal and radiation problems, and weight restrictions. When the general technique had been determined, the resultant circuit designs for the inverters were developed with efficiency, power to weight ratio, and reliability as key criteria. High efficiency was desired in order to provide maximum power transfer between the source, which usually has a limited amount of power, and the load. An increase in efficiency will also allow a decrease in the amount of heat sink weight and volume required for a particular inverter design. High power to weight ratios for these space inverters must be a major design objective in order to obtain more useful payload weight for a given launch vehicle thrust. A high reliability figure is manditory in order to provide long trouble-free service under the most adverse environmental conditions. However, for space applications where it is usually impossible to carry spare units or to perform routine maintenance for unmanned missions, the aspect Of inherent reliability must be weighted heavily against efficiency, and power to weight ratios in order to achieve an optimum inverter design. It was a purpose of this study to explore the interrelations of these various aspects of the space power conditioning problem in an effort to determine the most feasible techniques to fulfill the present and projected requirements for high power space static inversion and conversion equipments. In order to correlate the multitude of performance parameters for the inverters and their interrelationship with the components and the circuitry required for an optimum design, certain ground rules were established. These ground rules determined the best methods of evaluating the components and techniques so that the wide range of choice could be narrowed to a few selected approaches. The quantities of primary concern in this optimization study are listed below in three groups of the Methodology Plan. 6 METHODOLOGY PLAN GROUP I Nominal Description of the Inverter a) Full load volt-amperes (va) in a specified power factor range. b) Frequency c) Number of phases d) DC input voltage GROUP H Performance Specifications a) Harmonic distortion b) Variation of DC input voltage around nominal c) High frequency transients on DC input d) Output voltage e) Output voltage regulation, steady state and transient f) Output pha se separation g) Output short circuit protection h) Overload capability i) Unbalanced load capability j) Output frequency regulation GROUP III Parameters to be Optimized a) Weight b) Efficiency c) Reliability This list, while not all inclusive, does contain the quantities which are of primary concern to the electrical design of an inverter. They were split into three separate groups. These particular groups were selected in con- junction with the proposed ground rules which are discussed next. Group I determines the nominal requirements of the inverter. At the begin- ning of this program it was proposed that these characteristics be limited to the following ranges for three inverter types: GROUPI TYPE A TYPE B TYPE C Watt range Frequency Number of Phases Range of DC Input Voltage 100 to 500 at 500 to Z000 Z000 to 10,000 1.0 to .7lag 1.0 to .7 lag 1.0 to .7 lag power factor pow er factor power factor 400 400 3200 3 3 3 15 to 100 15 to 100 15 to 100 7 A program redirection was instituted later in this program which directed all efforts toward the development of an optimum design for (a) a 3200 cps, 10 KW inverter and (b) a 400 cps, 10 KW inverter, in place of the low and medium power 400 cps inverter requirements that were originally specified. The range of 15 to 100 volts was selected as the probable limits of DC voltage sources that would become standard in the future. For the conceptual designs 56 VDC was selected as the most feasible input voltage. Scaling techniques were developed which then allowed the system designer to see the variations in weight and efficiency that attended a change in VDC nominal. The selected inverter techniques will be capable of accepting a nominal (+ 10°/o, -20_0) voltage within these DC limits without a change in the general configuration. The choice of specific components was directly related to the DC voltage level under consideration. Inverters which operate from DC sources of one volt and under were considered to be outside the scope of this study. Studies indicated that this type of inverter is not especially suited for space applications because of its low power to weight ratio. Inverters which operate from high sources of DC voltage (i000 V DC and Higher) were also considered to be outside the scope of this study. However, because of the low currents involved, this type of inverter offered a potentially high power to weight ratio if suitable switching components and techniques could be developed. The Group ii performance specifications are listed next. Harmonic Distortion: DC Input Voltage Variation: High Frequency Transients on DC: Output Voltage : Output Voltage Kegulation: Output Phase Separation: Short Circuit: Ore rload: Unbalanced Load: Not to exceed 5% on total distor- tion with any single harmonic not to exceed 2%. + lO%, -z0% _200% of nominal for 10 micro- seconds or less 115/208 VAC ±Z°_0 for steady state, upper limit of transients during load switching to be +50% of normal envelope with recovery to steady state in 20 cycles. 120 =1=2degrees Automatic recovery to normal operation when short is removed. 200% for 5 seconds with ±4% regu- lation. Up to I/3 the total maximum VA between highest and lowest phases. One additional area which is difficult to treat as an exact specification but is nevertheless important is the effect of the DC source impedance. Solid state inverters use switching techniques to condition the raw DC power. This rapid switching causes the DC input current to contain AC components at multiples of the switching frequency. These AC components can cause transmission line disturbances as well as disturb the source itself. While these disturbances are essentially a detailed application problem, it is desirable to know approxlmately the time profile of the input current so as to ascertain the probable magnitude of the problem. Calculation of the input current to a transistorized inverter (under the assumption of zero source impedance) is relatively straight forward. The input current to typical SCR circuits was explored in enough detail to show the complexity created by the commutation currents involved in SCR circuits. Group IN, (weight, efficiency and reliability) represents those parameters which must be optimized for any specific mission. It was the primary purpose of the study to select the methods and components which wottld allow the Group III parameters to be optimized for the given inverter types. These Group IH parameters are usually interrelated in such a way that optimizing one of them will generally degrade the others. For instance, an extremely lightweight inverter might be designed to re d uc e the design margins on wound iron components. However, this would result in more heat loss in these components. This additional heat loss would reduce the efficiency and push the semiconductor components closer to their maximum operating tem- peratures thereby reducing reliability. The Group ILl parameters also interact with the Group II specifications. For instance, the lightweight inverter described above might also sacrifice harmonic distortion. These inter- relations between Group II and Gro'_p HI as well as the interactions of the Group ILl parameters with each other are analyzed in the main body of this study. The weight estimates of these conceptual designs were defined as the weight of the electrical components only. It will not include the weight of such things as heat sinks, outside case and other structural supports, connectors, etc. The weight of these additional items is closely related to the type of heat sinking that is available and the shock and vibration levels to be encountered. While it was beyond the scope of this study to determine the packaging con- figuration and hence total weight, a reasonable engineering estimate is that the weight of the electrical components will comprise 50% to 70% of the total weight in an aerospace type inverter. The reliability of any inverter is obviously very important. However, the number attached to the concept of reliability is a quantitative expression of 9 the effect of such factors as the number of components used to perform a certain function; the temperature, voltage and current stress on these com- ponents; the intrinsic reliability and failure modes of the components them- selves; and the number of redundant circuits or components that are used; and the required life of the mission. Most of the above information can be obtained from a theoretical analysis. However, the actual stress levels must be measured onbreadboards, etc., before a number can be assigned to the actual circuit reliability. Moreover the temperatures of the components, especially the semiconductors, are a function of the packaging and cooling of the final unit. These factors combine to make any discussion of absolute reliability strictly an academic discussion if the stress levels existing in the final package are unknown. During the initial phases of this study the voltage and current stress levels were approximated by analysis and judgment based on the behavior of similar circuits. This analysis together with the relative number of parts in the various circuits guided the selection of the techniques to be studied intensively. In the later phases of the study an absolute reliability analysis was performed. This analysis will be based on assumed voltage and current stress levels in the conceptual designs. The temperature of the components, especially semiconductors, was also assumed to remain within a specified band. The effect of radiation on the reliability of an inverter was beyond the scope of this study. However, in selecting the components, radiation of Van Allen Belt intensity was assumed. Having established a basic set of performance specifications consistent with the reliable operation of an inverter in a space environment, the first phase of this study was directed toward a selection of the most feasible approach for each projected application. The primary consideration was a selection of the power stage for the inverter. Toward this end an investigation was conducted on existing designs for both series and parallel inverters in an effort to determine their operating ranges and their inherent strengths and weaknesses in regards to these established ground rules. I. INVESTIGATION OF EXISTING INVERTER DESIGNS A general description of present inverter configurations was examined next. These inverters were designed almost exclusively around two types of switching elements; silicon controlled rectifiers (SCKls) and transistors. The difference between these, of course, was the lack of ability to turn off the SCR at the gate. An external means must be provided to reduce the current in the SCR to zero. Series type inverter circuits were investigated first. These circuits used SCR's alrnost exclusively thus requiring additional circuitry to turn these SCR's off. The results of this investigation revealed that the series type inverters were limited in useful load range to approximately 3 to 1. No 10 simple circuit modifications appeared to be available to extend this useful load range ratio, therefore, no further effort was devoted to these series inverter circuits. Instead, parallel type inverter circuits were studied. The basic parallel inverter circuits used either transistors or SCR's as their switching elements. Again additional circuitry was required to turn off these SCR's that were used as the switching elements. Technical information for parallel inverter operation with both resistive and inductive loads were avail- able in the literature and were studied extensively. However, the technical information did not include the operation of the inverter under unloaded or switched conditions. Therefore, a detailed analysis (See Appendix 4-I) was performed for this unloaded or switched condition with the results that this parallel inverter would not operate properly because the only current path for the reactive current to flow was through the commutating capacitor under these conditions. Improve- ment of this basic parallel inverter circuit was realized with the addition of "reactive" diodes to provide an alternate path for this reactive current (the McMurray-Bedford Circuit}. This allowed the inverter to operate at all load power factors. These "reactive" diodes also limited the voltages under no- load conditions, thus making inverter operation under no-load conditions possible. However, should the load current become too large, resulting in excessive currents at the time of commutation, the turn-off time of the inverter is decreased causing the inverter to malfunction. A comparison was made between the various types of SCR inverters with respect to several parameters such as weight, efficiency, etc., (see Table 4-I}. These parameters were based on 400 cps inverters with 5% total harmonic distortion and operating at the 1 KW level. The results showed that for fixed load operation, the series inverter was superior, but for large load variations, the McMurray Circuit was favored. The output voltage of all the inverters mentioned previously was a direct function of the D.C. input voltage and could be varied by changing this input voltage. Thus, some type of voltage regulator will be required to regulate the inverter output voltage. Different types of voltage regulators were investigated in order to determine their individual merits when they were used with these inverters. The simplest type of D.C. regulator was the series proportional D.C. regulator which used a series transistor in the input of the inverter to be regu/ated. This type of regulator was only efficient when the input voltage to the regulator was very close to its output voltage in order to minimize the power loss in this series transistor. The input voltage excur- sions to this regulator must be kept small in order to maintain this high efficiency. Thus, the series proportional D.C. regulator could only be used to regulate low power inverters whose input voltage variation is small. 11 A modification of this series proportional type of voltage regulator was the series switching D.C. regulator. Here the series transistor was used as a switch that could be turned full "on" or full "off" depending on how the output voltage compared with a reference. This type regulator required an LC filter to smooth out these D.C. output pulses. The size and weight of this LC output filter was depended on the switching frequency of this regulator which in turn was determined by the maximum switching times of the series transis- tor chosen. The efficiency of this regulator was good under all load conditions within the rating of its series switching element. This regulator could accept large input voltage excursions which were only limited by the conduction angle swing of the series switching element. The size and weight of the LC output filter required to smooth these D.C. output pulses to an acceptable level limited its use for regulating high power inverters. Both these series switching type regulators had one disadvantage in common in that their output voltages could be no greater than their input voltages. It becomes desirable in some circuit applications to have the regulator output voltage larger than its input voltage. Such step-up in voltage levels were required in inverter schemes that do not employ transformers in their output power stages such as the pulse width modulated type of inverter. A shunt1 switching type of D.C. regulator developed by Bedford will produce a regulated Do C. output voltage that is greater than its input voltage. This type of circuit depended on the controlled energization of a series inductor through a shunt switching transistor whose switching time was controlled by an error signal in the same manner as was used for the series switching regulator approach. The operation of this circuit was highly dependent on the values of inductance and capacitance used for a given load range. These reactive elements could become quite large for large load requirements. A common method that was used to obtain a step-up or step-down in the D. C. voltage level of the D° C° source was to first change it to an A. C, square wave with a simple parallel inverter. The A.C. output of this parallel inverter could then be stepped up or down by simply varying the turns ratio of the inverter transformer. Regulation was obtained by either controlling the amplitude or turn "on" and turn "off" time of this A, C. waveform. The regulated output D. C, voltage level was obtained by rectifying and filtering the A, C. wave- form output of this inverter. A modification of this basic inverter-regulator-rectifier circuit was to provide only the difference voltage between the D.C. source and the desired D. C. output voltage. This was accomplished by connecting the output of this regulator circuit in series with the source to provide this regulated difference output. Therefore, the inverter-regulator was required to pass only the error 1 Quarterly Progress Report #4 on "Voltage Regulation and Power Stability in Unconventional Electrical Generator Systems" (ASTIA #ADZ65158)page 87. 12 power instead of the total D. Co source power making it less complex and more efficient than the basic inverter-regulator-rectifier circuit approach. In the above discussion separate regulator circuit approaches were considered in order to regulate these high power static inverters. It was possible with certain types of high power static inverter designs that required output transformers to incorporate voltage regulation as part of their power output stages. Regulation could be accomplished by phase shifting one square wave with respect to a fixed square wave, both generated by this power stage, to produce a simple quasi-square wave whose resultant amplitude could be varied to provide this regulation. Suitable output filtering was required to suppress the harmonics generated by this quasi-square wave. More sophisti- cated approaches could be taken by generating multi-stepped waveforms with less harmonics that could be phase shifted in order to reduce the size of the output filter components required to suppress the resultant harmonics that were generated. Two basic regulator approaches have been presented that could be used to regulate these high power static inverters. The first regulator approach required a separate regulator that either steps up or steps down the D.C. source voltage to the power stages of static inverters which usually do not have output transformers. The second regulator approach was included as part of the static inverter power output stage which usually has an output transformer. Regulation was usually accomplished by phase shifting one A.C. waveform with respect to a fixed A° C. waveform. In either approachp the harmonic distortion of the unfiltered outputs of these high power static inverters was usually too large, Thus, these harmonics must be removed by either filtering them or by using circuits which will produce harmonic cancellation. The optimum design was usually a combination of these two. II. 3200 CPS - 10 KW STATIC INVERTER DESIGN CONSIDERATIONS With this background of the type of basic inverter circuits available, along with their significant characteristics, such as output voltage waveforms, allowable loads, and methods that could be used to regulate their output voltages, a study was made of the possible approaches to any of the inverter groups described in the Methodology plan. Since this Methodology plan had been revised to eliminate the inve stigation of both the low and medium power -400 cps Static Inverters, all efforts were directed toward determining optimum circuit configurations for both the 400 cps and 3200 cps high power (10 KW) static inverters. The problem of the 3200 cps - 10 KW static inverter was considered first as it appeared to be the most difficult and no specific approaches appeared to offer a clear advantage. A survey of inverter config- urations and switching devices was undertaken and representative inverter 13 circuits analyzed. It was felt that there were two basic design decisions to be made. One was the selection of the basic power switching stage and its power switching elements. The second was the technique of combining these basic elements to obtain a three phase, voltage regulated sinusoidal output whose characteristics would conform as close as possible to the specifications outlined in the Methodology plan. The various switching devices were investigated first to determine their merits and disadvantages when used in different high power static inverter configurations. They were germanium and silicon power transistors, silicon controlled rectifiers, and gate controlled switches. Two basic power inverter approaches were considered for this 3200 cps - 10 KW inverter design. They were high frequency pulse width modulation techniques and quasi-square wave or stepped wave techniques. The pulse width modulation scheme was found to be impractical at this operating frequency since its minimum practical carrier frequency would be approxirnately five times the fundamental or 16,000 cps. Neither the silicon controlled rectifiers nor the gate controlled switches had fast enough turn "on" and turn "off" times to handle these switching speeds. Germanium transistors cf sufficient current capacity to minimize the number of parallel transistors required per half phase to a reasonable number could not be obtained with sufficient switching speeds to accommodate this carrier frequency. Medium power silicon transistors (10A) were found with extremely fast switching times that could accommodate this carrier frequency. However, the resulting switching losses of 130 watts per transistor at 16,000 cps and 200% load were found excessive for a reasonably efficient power stage. Thus, the pulse width modulation approaches were considered to be impractical at this operating frequency of 3200 cps. The second approach to this problem would be to perform the inversion at the fundamental frequency of 3200 cps, thus reducing the switching losses that were obtained for the pulse width modulation schemes. Again the various switching devices were compared with the results that both the silicon controlled rectifiers and gate controlled switches were found unsuitable for high power inverter applications. The gate controlled switches were limited by their low current ranges (6A maximum) and their rather long switching times. The silicon controlled rectifiers were available in ratings up to 400 arnps rms and voltage ratings up to 1300 volts. However, the fact that the silicon controlled rectifiers must be commutated off by an external source adds circuit com- plexity and additional losses at these high power levels. From a weight point of view, this additional weight required by the many transistors over a few silicon controlled rectifiers would be compensated by the elimination of the commutating capacitors and chokes required by the SCR circuitry. The higher efficiency of the transistorized devices and absence of the high peak currents 14 associ_ed with the silicon controlled rectifier commutation would reduce the size and weight of the output transformers and heat sinks of the proposed power inverter. Comparing the germanium and silicon transistors for this stepped wave inverter approach at 3Z00 cps revealed that for a given transistor current capacity the silicon transistor would have approximately i. 5 times the losses as an equivalent germanium transistor. The major loss in the silicon transistor was contributed by its forward losses. In the germanium tranststor_ however_ the major loss was due to its switching losses. ]_ would appear that the germanium transistor would offer a better choice. However, its maximum junction temperature was limited to I00 * C while the silicon transistor Junction temperature was good to 200eC_ thus requiring less heat sink capacity. In addltlon_ silicon transistors were available in ratings up to 150 amps rrns with ratings to 150 VCE. These were much larger ratings than could be obtained for germanium transistors at this time. Thns_ fewer silicon tran- sistors would be required to perform the same switching function. The selec- tion of silicon transistors for the power stage switching elements were made because of these two reasons. In order to reduce the silicon transistor losses in this power inverter_ possible circuit changes including techniques for optimizing the switching pattern_ reducing the curre_ and/or voltage at the time of switching, or reducing the effective switch resistance by connecting additional transistors in parallel could be utilized. Transistor drive losses could be reduced by providing a current feedlmck drive control which would be proportional to the instantaneous collector current rather than a voltage square wave drive whose output was fixed for the largest collector current. Since the stepped wave approach was decided upon for the 3Z00 cps - 10KW static inverter_ an analysis was performed on various stepped waveforms to obtain a maximum number of harmonic cancellations for a minimum amoun_ of circuit complexity. The more harmonics that could be effectively can- celled would in turn reduce the size and weight of the filter components required. The method of voltage regulation would be a major factor in selecting the stepped waveform to be used. It was found that adding together two multi- stepped waveforms with a variable phase difference in the power stages would produce the most efficient and lightweight means of regulation which would produce a minimum harmonic distortion. A _ariety of stepped waveforrn characteristics that have been proposed by contributors to the field of static 15 inverters were investigated. The various waveferms were classified as to the number of horizontal steps that could be counted in a full cycl% whether the steps occurred at equal or unequal time intervals and whether the step heights had equal or unequal amplitudes. The stepped waveforms examined were broadly classified into two groups. The first group were waveforms that could be divided by the smallest time increment step into an integral even number of parts. These waveforms had steps of optimum height that specifically reduced the number of lower harmonics. The second group of stepped wave- forms were those which had been specifically designed to have either the minimum total harmonic distortion possible for a waveform having a particular number of steps or designed specifically to eliminate certain harmonics. The application of the stepped waveforms to static inverters required certain characteristics of the waveform for three phase operation. In some of the waveforms examined, a single square wave inverter could supply two or even three phases with a required step and therefore was given additional considera- tions. Thus, waveforms requiring no increase in the number of basic square wave inverters to generate three phases compared to the number required by a single phase inverter were chosen. From these waveforms_ the ones whose phase voltages could be connected in a delta configuration were given special consideration. This narrowed the choice of multi-stepped waveforms down to three choices using the above criteria. They were: 1) Six steps per phase requiring three inverters per phase with the fifth harmonic being the lowest. 2) Twelve steps per phase requiring six inverters per phase with the eleventh harmonic being the lowest. 3) Eighteen steps per phase requiring nine inverters per phase with the seventeenth harmonic being the lowest. Of these three, the waveform containing twelve steps requiring six inverters per phase was chosen. This required an output filter capable of suppressing the eleventh harmonic and its complement, the thirteenth. Although the selection of the eighteen step waveform would permit a further decrease in filter size_ the increase in circuit complexity required with the use of nine inverters per phase would not Justify the increase in weight and loss in efficiency that would occur. Thus, the waveform containing twelve steps per phase was considered an optimum choice for this 3200 cps - 10KW static inverter. Having established the type of stepped waveform that would be used in the power output stages for the 3200 cps - 10KW static inverter, a concentrated 16 effort was devoted to the magnetic components that would be used in this static inverter. A detailed study was undertaken to obtain optimum magnetic com- ponent designs. Optimum magnetic designs required not only optimization of the individual magnetic components for a given inverter design, but also pro- vided an optimum choice of the overall system that would eventually be used. An optimum magnetic component design would depend on the specific applica- tion since, in general, weight and losses could not be minimized together. Optimum loading of a fixed transformer was investigated first. The general rule regarding the optimum loading of a transformer was that maximum efficiency occurred when the core and copper losses were equal. However, this rule was based on the conditions of a constant input voltage and a variable load. If both, the input voltag e and maximum design load were fixed, which was usually the case, then the 0nly parameters that could be varied were its physical size and its relative losses in the windings and core. Maximum transformer efficiency for this case was found when the core loss was not quite equal to the copper loss. However, the actual differences in these losses were not very large so the general rule mentioned previously still applied. A general set of equations were developed next to permit an optimum transformer design for a given power level to be scaled to a different power level with respect to volume, weight, and losses. This would enable new transformer designs to be obtained without extensive calculations. These general set of equations could only be used to compare transformers of similar construction operating at the same core flux density and copper current density levels. They were used extensively when the final 3Z00 cps - I0 KW static inverter design was scaled to lower power levels. An analysis was made on the losses of transformers delivering constant power as their size and weight were varied. The results of this analysis indicated that for a fixed power level, a transformer with a minimum weight loss pro- duct could be obtained when its core material was operated as close to its maximum flux density as possible. The analysis of transformer optimization was expanded to include its associated circuitry when the three phase power output transformers were considered. Various possible power switching stages which could be used for this 3200 cps - I0 KW static inverter were investigated. It was found that some required the use of three single phase transformers, some required one three phase trans- former, and some required more complex transformer construction. Since a twelve step, six inverter per phase waveform was decided upon, a comparison of the many possible transformer configurations that would be compatible with *_his waveform was undertaken. It immediately became clear that the three phase transformer had less volume and weight than three single phase trans- formers with equivalent three phase capacity. However, the circuit complexity 17 required to drive this three phase transformer more than offset these advantages obtained in both weight and volume reduction. A more complex transformer suitable for op_ration with this twelve step waveform had been described in the literature. This transformer contained six windows whose outer legs supported both the primary and secondary windings. This trans- former was referred to as a "hexadic" transformer because it contains six windows. This "hexadic" transformer obtained its weight savings by using less iron in those portions of the magnetic circuit where flux cancellation occurred. It was estimated that the "hexadic" transformer was approximately 20% lighter than its six single phase counterparts. This analysis was extended to include several possible complex transformer designs similar to the "hexadic" transformer. Again, the same basic technique of flux cancellation was utilized in different portions of the magnetic circuit to reduce the weight of these transformers. Additional flux cancellation was also obtained when the phase shift between the two sets of multi-stepped output voltage wave- forms was varied to obtain voltage regulation. A transformer suitable for use with this twelve step waveform was conceived. It contained twelve windows arranged in two rows of six and was designed for minimum core weight. The primaries for both the reference twelve step waveform and the phase shifted twelve step waveform were wound on the six outer legs of each side of the transformer respectively while the secondary windings were wound on the six inner legs which were common to the twelve windows. Two "hexadic" transformer cores would be required to provide this twelve step waveform phase shifting regulation scheme. A comparison between this proposed transformer and the two "hexadic" trans- formers based on the same core cross-sectional area and window area per winding revealed that the two "hexadic" transformer cores have 96.5% of the weight of the proposed transformer core. However, when the winding weights were factored in, the total weight of the two "hexadic" transformers became 1.63 times the weight of the proposed transformer. Both these designs were too heavy in winding weight as compared with their respective core weights, and improvements in both could be expected with a more detailed design effort. Thus, the proposed flux adding transformer design with twelve windows was the choice for this 3200 cps - 10 KW static inverter. The core material and operating flux density were considered next for this transformer. Three types of core material were considered. They were Square Permalloy 80, Orthonol, and Supermendur. A sample transformer 2"Static Inverter with Neutralization of Harmonics", A. Kernick, J. Roof, T. PIeinrich, AIEE Transactions, May, 1962, pp 59-68. 18 was designed using each of these core materials. They were theoretically operated at various frequencies and power levels. These sample transformers were simple two winding toroidal units with equal copper and core weights. The maximum flux density that the transformers could support was considered the design limit. The results of this investigation were tabulated for five selected frequencies and were used to optimize the output transformer design at 3200 cps. A final 3200 cps transformer design was made for each of the three core materials. All three transformer designs were obtained by operating the core materials at their maxtmurn flux density levels. The results of their weight loss products and efficiencies were: DESIGNS I II III Sq. Perm-80 Orthonol Supermendur (2 rail) (2 rnil) (2 rnil) (79% Nickel} (50%0 Nickel) (49W Iron) (17% Iron) (5070 Iron} (2% Vanadium) (4% Molybdenum} (49% Cobalt) WT-LOSS PRODUCT 1860 lb-watts 1300 lb-watts 9 75 lb-watts EFFICIENCY (at I0 KW load) 99.16% 98.37% 96.32% From these results, the Orthonol core material was selected for the final transformer design since it was in between the two extremes of weight and efficiency. The silicon transistor switching elements that would be used for these output power stages were determined next. Calculations indicated that the peak load current that would have to be carried by any one side of a power switching stage would not exceed 88 amps for a Z00% overload condition. The peak voltage appearing across any of the power switches would occur at turn- off and would not exceed 133 volts. Both these current and voltage require- ments could be satisfied by one power transistor whose ratings were 150 amps and 150 volts. Although this transistor had sufficient current capacity, its voltage level did not offer much safety margin. Larger voltage ratings for this transistor are expected in the near future which will improve this safety margin. If larger voltage safety margins were desired than could be provided by this transistor, then it was possible to series two of these transistors per switch leg or to parallel a number of lower current higher voltage transistors. In either case, the circuit complexity and losses would present additional design problems; thus, the one 150V - 150 amp power transistor was tentatively 19 used for these switching elements and would be replaced with their higher voltage counterparts as soon as they become available. Having established the power stage output transformer design and the silicon transistor switches that were to be used with it, further means of improving the power stage efficiency were investigated, The results of this investiga- tion revealed that the power stage efficiency would be improved in two ways. The first improvement would utilize a timing core in the collectors of each of the power transistor switching pairs which would reduce their "turn on" losses to a negligible value. The resulting savings of 6 watts per output stage or a total of 72 watts for the entire inverter would be realized with the use of these delay cores. The second improvement would employ current feedback as a means of supplying the required transistor base drive in place of the more conventional voltage base drive scheme. A base drive proportional to the transistor collector current was obtained inthis current feedback scheme. The transistor base drive transformers in this case would be used as current transformers. In order to turn off a transistor it was necessary in this scheme to provide enough turn-off current on a pulse basis from an external driving source to completely cancel the positive drive signal from the collector feedback winding. The power wasting base current limiting resistors required for the conventional voltage base drive scheme were also eliminated. A savings of 320 watts total at full load had been estimated for this current feed- back scheme. Thus, a total savings of 392 watts had been realized with the use of these two schemes. The A.C. output filter circuit configuration and component values were deter- mined for the three phase outputs. Because of the widely varying load impedance encountered, conventional filter design techniques were not appli- cable for use with static inverters. The AC output filter must have a nearly constant phase shift and voltage transfer ratio over a wide variation in load impedance. Thus, a four element filter circuit was decided upon which con- tains a series tank circuit in series with the load and a parallel tank circuit shunting the load. The series tank resonance frequency was tuned to the fundamental frequency so no attenuation or phase shift would be encountered. This filter must reduce the eleventh and thirteenth harmonics to less than 2% each and the filter components were calculated accordingly. A D.C. filter was placed on the input terminals of this inverter in order to make the D.C. source appear "stiffer" to the inverter and to help attenuate the radio frequency noise impressed on the supply lines caused by the inverter current pulses. This D.C. filter consisted of a large capacitor (e, 100 ufd) that was shunted by a small (co. 01 u/d) mica capacitor. 2O The resultant weights and losses were determined for this complete 3200 cps - 10 KW p_wer stage and were found to be 29.55 pounds and 635.9 watts full load Io ss. The low level logic and power stage circuitry was tentatively designed for this 3200 cps - 10 KW static inverter. A complete set of schematics and parts lists were generated for this design. Since this circuitry and their parts were created from a theoretical design, they could only be considered as representative of the actual circuitry that would be needed since much bread- boarding of the individual circuitry will be required in order to finalize this design. The low level logic circuitry necessary to control the power stages will be described briefly. A master crystal controlled oscillator and pulse shaper circuit was used to provide a series of pulses at twelve times the fundamental frequency of 3200 cps to one six phase ring counter that was used as a reference, and a phase shifter circuit that was used as part of the phase shifter regulator scheme. The reference ring counter consisted of six inter- counected flip-flops whose outputs produce 6 square waves which were displaced 30 ° from each other and have a frequency of 3200 CpSo The outputs of this reference ring counter were used to control six pre-buffer drive stages which were composed of push-pull center tap transistor drive circuits. These six pre-buffer drive stages in turn controlled the six power stages which were used to generate the twelve step, three phase reference waveform in the inverter output transformer. The phase shifter circuit was made up of six cascaded stages each of which was capable of producing a maximum phase shift angle of 30 °. A typical phase shifter stage consisted of an input flip-flop, two linear ramp generators, a level sensing Schrnitt trigger, and an output flip-flop. The Schrnttt triggers had their voltage trip levels set for a pre-determined value. The input error signal from the output voltage sensing circuitry was introduced into the inputs of these Schmitt triggers. This input error signal current biased the linear ramps that appear on the input of these Schmitt triggers, shifting them up _r down with respect to the preset trigger levels. This caused the Schmitt triggers to fire at different points on the ramps as a function of the magnitude and polarity of this input error signal. A relative phase shift angle of up to 180 ° was obtained between the output pulses of the master crystal controlled oscillator and the resultant output pulses of the phase shifter. The phase shifted output pulses of this phase shifter were introduced into the input of a six phase ring counter that was identical in construction and operation to the reference ring counter. The outputs of this phase shifted ring counter were used to control six pre-buffer drive stages. These pre- buffer drive stages in turn controlled the six power stages which were used to 21 generate the phase shifted twelve step, three phase waveforms in the inverter output transformer to provide the necessary voltage regulation. A short circuit current limiting circuit was provided to protect the inverter against overload currents exceeding 215%. This was accomplished by turning off the power stages for a finite time and then turning them back on. This cycling would continue as long as the short remains, thus protecting the inverter components. A reliability study was performed on the electrical circuitry and their parts for the proposed 3200 cps static inverter. This reliability study could only be used as a guide since this circuitry was created from a theoretical design and the stress levels assigned to each component were based on this theoretical design with no actual stress measurements being taken. Packaging techniques and electrical connections were not included in this reliability study. The parts failure rate approach was used to analyze each component in this electrical system. A reliability block diagram was used to represent the overall circuit configuration. Each major circuit was represented by one of these blocks. A series of sub-blocks were assigned to each major block to represent the individual circuits or components that were required to create a major circuit. This reliability block diagram was used with the representative circuits for each sub-block to establish an overall Reliability Figure of Merit R for the 3200 cps - 10 KW Static Inverter. The generic failure rates, derating factors, and environmental operating modes for the electrical components were obtained from: "Reliability Engineering Data Series Failure Rates" by D. R. Earles, M. F. Eddins. Avco Corporation - Research _ Advanced Development Division. The operating time for each component was determined. From this informa- tion the overall Reliability Figure of Merit R was computed for a 20-minute missile launch combined with one month and then one year continuous operation as a Satellite in an earth orbit. The results of this study indicated that this inverter would have a reliability of . 963506 and .718930 for the one month and one year continuous operation respectively. There were no redundant circuits in this proposed inverter. In order to improve its overall Reliability Figure of Merit, redundant circuitry should be used with circuits that contain the largest failure rates. Components with larger de-rating factors could also be used to improve these reliability numbers. The last area of investigation for the 3200 cps - 10 KW Static Inverter involved scaling its weight, losses, and reliability with respect to reduced power level, 22 D.C. input voltage, harmonic distortion, output phase separation, voltage regulation, and D.C. input variations. The effects of scaling this inverter with respect to reduced power level and D. C. input voltage were of primary interest. As the power level was reduced below I0 KW, there were a multi- tude of changes which occurred in the inverter components and circuitry. Components such as transformers, inductors, etc., which must be especially designed for a given inverter could be scaled for loss and weight on a con- tinuous basis. However, components such as transistors and diodes which were not made specifically for a given size inverter but were selected because their parameters met or exceeded those required for a particular application would vary in a step component change. There were also certain components and circuits which were independent of the power level such as the master crystal controlled oscillator and pulse shaper circuit. Weight and loss curves as a function of power level were obtained for these magnetic and semicon- ductor components. The total weights and losses for all these components were added together to obtain the anticipated weight and loss of the entire inverter as a function of the power level. The weight and loss of the magnetic and semiconductor components were determined as the D.C. input voltage was varied. The power stage transistors were found to be the components most affected by these voltage changes. When the D.C. input voltage was dropped below 41 volts, the current in the power stage transistors became excessive, thus requiring paralleling techniques to reduce these currents to an acceptable level. The paralleling of these power stage transistors modified the power output transformer so that a split transformer technique was required. As the nominal D.C. input voltage exceeded 68 volts, the power stage trans- formers were connected in a bridge configuration to allow each transistor to support half the D.C. input voltage. Again, the total weights and losses for a]/the inverter components were added together to obtain the anticipated weight and loss of the entire inverter as a function of the D. C. voltage input level. The scaling involving harmonic distortion, output phase separation, voltage regulation and D.C. input variations revealed that the A.C. output filter parameters were the components most effected_ The output power trans- former copper loss and leakage inductance were reflected as part of the filter parameters. Also, the load impedance was considered as part of these filter parameters. Weight and loss curves were determined for each of the filter components as the above four parameters were varied. The worst condition that was encountered was the effects of unsymmetrical loading on the voltage regulation. If the voltage regulation tolerance was reduced below _2%, an individual voltage regulator would be required for each phase which would require three separate power flu_-adding transformers with an increase of weight and losses over the present system of 2.32 lb and 55.5 watts. In addition, three times the power switching transistors and pre-drtve circuitry 23 would be required along with two additional ring counters, two phase shifters, and two voltage sensing circuits. This added circuit complexity did not justify reducing the voltage regulation tolerance below ±2%. A detailed design study had been completed for the 3Z00 cps - I0 KW Static Inverter. A conceptual design was created using the Methodology plan as a design guide. Many inverter designs, circuit approaches, and component optimization studies were investigated in regards to efficiency, weight, and reliability as well as other design parameters listed in the Methodology plan before this inverter design was established. Improvements in efficiency, weight, and reliability should be realized if this conceptual design is fabricated since new circuit approaches and more optimum component designs will develope as experience is gained with the various circuits. Assuming that the 3200 cps - 10 KW design is performing to the Methodology plan, a detailed reliability analysis may then be instigated in which the electrical and thermal stresses of each circuit component are carefully measured. The overall reliability can then be computed with a high degree of confidence. Reliability recommendations may be incorporated into the circuitry wherever possible to improve the inverter's reliability figure of merit. The component weights and sizes may also be computed accurately. Such items as heat sinks, terminals, connectors, etc., which were intangible items in the theoretical design may now be accurately determined in order to obtain a final package configuration. Shock, vibration, and other environmental conditions must also be considered for this final package design. At present, the conceptual design offers a lightweight (/_41.5 lb total com- ponent weight) and an efficient {r,-92% overall at full load and . 9 P. F. ) inverter. However, its overall reliability figure of merit (R_'. 71893 for one year continuous operation as a Satellite in an earth orbit) will have to be improved considerably either through the use of redundant circuitry or with less complex circuit designs. A miDimum safety factor margin of two was used-for a design goal in this theoretical design wherever possible. Circuits which employ components that cannot meet this design goal should be thoroughly investigated in order to determine alternate approaches that can be used. For example, the power switching transistors that are presently available only allow for a safety factor of 1. 125. Thus, either higher voltage units of 150 amp capacity must be found or lower current transistors with higher voltage ratings must be paralleled. Overvoltage circuit protection may also be used to protect these transistors. Therefore, the conceptual design that was determined, will require more design considerations coupled with extensive breadboard testing of the individual circuitry before an optimum 3200 cps - 10 KW static inverter design can be realized whose electrical parameters will either conform or exceed those defined in the Methodology plan. 24 IIL 400 CPS - I0 KW STATIC INVERTER DESIGN CONSIDERATIONS The 400 cps - 10 KW Static Inverter Design was investigated. Both the Multi-Stepped Waveform techniques which were described in detail for the 3Z00 cps inverter design, and the Pulse Width Modulation techniques were considered for this 400 cps - 10 KW inverter design. The Pulse Width Modulation techniques consisted basically of switching hi-polar high voltage Do Co to produce duty cycle controlled pulses at the carrier frequency to synthesize the 400 cps sinewave. (The carrier frequency of 10 KC has been selected for this inverter design.) These two approaches were capable of producing an output waveform that contained only the higher harmonics therefore requiring a simple and light weight A. Co filter. The most pre- dominant frequency for the Pulse Width Modulation approach was the carrier frequency. The first harmonic pair for the Multi-Stepped Waveform approach was pre- dominant with their frequencies determined by the number of steps selected. The Multi-Stepped Waveform approach required a multi-phase output trans- former and its associated switching transistors connected in push-pull pairs which must be capable of producing 10 KW at an operating frequency of 400 cps. The Pulse Width Modulation approach departed from the more conventional Multi-Stepped Waveform approach by not using any form of power trans- former in its output stages. Instead, the Do C. source voltage was stepped up to a bi-polar high voltage level by a rather simple DC-DC converter which used a light weight output power transformer. This bi-polar high voltage D. C, was then sent to the power stages which consisted of power transistor switches that were connected in parallel for each half phase to obtain the required current capacity. Six of these half phases were required to produce the necessary four wire, three phase output. The power transistors were connected directly to the load with their "on" and "off" times controlled by the driver stages. The resultant output voltage waveform, before the A.C. filters, was a series of pulses whose "on" and "off" times synthesized a 400 eps sine- wave with the carrier frequency being the predominant harmonic that must be eliminated. The Pulse Width Modulation scheme was selected for this 400 cps - 10 KW inverter. This selection was based primarily on a preliminary comparison of weight, efficiency, and reliability between the Pulse Width Modulation scheme and an equivalent inverter using the multi-stepped waveform approach. The results of this preliminary comparison indicated that a weight savings of 57. 4 pounds would be realized with the use of the Pulse Width Modulation scheme (PWM_,150 lbs and Stepped Waveform_207.4 lbs). However, the efficiency of this Pulse Width Modulation approach was slightly less (PWM z_'8Z. 4% and Stepped Waveform/_-83.5_0). Z5 The reliability figures were not known at this time since the detailed designs had not been performed. Thus, for selection purposes, the reliability of the two approaches were assumed to be the same. The selection of the Pulse Width Modulation scheme was then based on the apparent weight savings of 57.4 pounds since the efficiency variations between the two approaches appeared to be negligible. An examination of the electrical parameters (Group If) of the Methodology plan did not reveal any characteristics which might be better in one system rather than the other with the exception of short circuit protection. The Pulse Width Modulation approach would provide faster short circuit protection by changing its index of modulation because the output filter requirements were less. A DC - DC converter was required for this Pulse Width Modttlation scheme to step up the source voltage to a bi-polar high voltage output that was required for the output power stages. The efficiency of this DC - DC converter was calcttlated to be 88a/0 while the efficiency of the actual inverter was calculated to be 93.5_/0. If the converter was eliminated by using a bi-polar high voltage source, then the overall inverter efficiency would then become 93.5a/0 making this inverter approach even more attractive. A detailed investigation of the various high frequency Pulse Width Modulation techniques was undertaken in order to determine which one would produce waveforms with low total harmonic content with relatively simple inverter circuitry. All these Pulse Width Modulation techniques operated by modulating the width, phase, or frequency of a high frequency carrier signal with a power frequency and then demodulating the resulting waveform to obtain the rnodu- lating frequency power. The Classical Pulse Width Modulation technique was examined first. Its output voltage consisted of a number of pulse duration modulating pulses having their trailing edge modulated by a power frequency. The method of analyzing these complicated waveforms was developed by W. R. Bennett 5 and consisted of a double Fourier series that represented this waveform, Tnis method of analysis was applicable to both uniform and natural sampling techniques wi_h modifica- tions. In the uniform sampling technique, the pulse width was proportional to the instantaneous value of the modulating wave at uniformly spaced sampling times. An analysis of its waveform spectra revealed that the method of uniform sampling had a carrier and its harmonics and sidebands that diminished rapidly. In addition, this waveform contained second, third, fourth, fifth and sixth harmonics of the power frequency which would require a rather large and heavy filter to eliminate them. Thus, the method of uniform sampling would not produce a waveform with low harmonic content that would allow a light- weight filter to be used. 3 W. R. Bennett, "New Results in the Calculation of Modulation Products". System Technical Journal, New York, Vol. Z8, No. 3, pp 490-595. Z6 the Be / Natural sampling was investigated next. In this case the pulse width was a function of the average value of the modulating waveform during the sampling interval. Examining the natural sampling spectra revealed that the carrier and its harmonics and sidebands were identical to those of the uniform sampled technique. However, there were no lower harmonics of the power frequency as occurred for the uniform sampled technique. Thus, a simple lightweight low pass filter could be used to filter the carrier and its side- bands. The method of natural sampllng produced a waveform with lov_ har- monic content with rather simple inverter circuitry. The Commutated Pulse Width Modulation techniques were also examined. Both natural and uniform sampling could be used with this technique. In this technique, the modulating wave was first rectified and then operated on by the modulator. The resulting pulse width modulated waveform was then comrnutated by a square wave which was in synchronism with the modulating waveform. A triple Fourier series expansion was required to analyze this waveform. The results of this analysis revealed that the harmonic spectrum of both the uniform and natural sampling for this C0mmutated Pulse Width Modulation Technique was nearly identical to the harmonic spectrums obtained for the Classical Pulse Width Modulation technique. The choice of Modulation technique was based on the complexlty of the circuits required for each method. Each modulation technique required a loglc stage, a power inversion stage, DC - DC converter, and an output filter. However, the Commutated Pulse Width Modulation techniques required a demodulator stage and its associated logic circuitry. The modulating techniques employing uniform sampling were disregarded because of the heavy output filters required. The Classical Pulse Width Modulation technique employing natural sampling was selected for this 400 cps - 10 KW inverter because it had less circuit complexity than the Commutated Pulse Width Modulation technique using natural sampling. It was felt that the additional weight and loss obtained_for the Commutated Pulse Width Modulation technique did not justify the slight, if any, reduction in output filter weight that could be obtained. Having selected the Classical Pulse Width Modulation technique with uatural sampling for the 400 cps - I0 KW static inverter, the various switching devices were investigated. The Pulse Width Modulation scheme required a minimum practical carrier frequency of twenty-five times the fundamental or i0, 000 cps so that the frequencies of the carrier and its harmonics and sidebands would be high enough to allow lightweight filter components to be used. The results of this investigation revealed that neither the silicon controlled rectifiers or gate controlled switches have fast enough switching times. Germanium trans- istors of sufficient current capacity for reasonable parallel operation also had switching times that were too slow for efficient operation. However, 27 medium power silicon transistors (IOA) with high voltage ratings had been found with extremely fast switching times that could accommodate this carrier frequency (10,000 cps) with a minimum amount of switching losses. In addition, transistors with high switching speeds would allow a maximum value for the modulating wave component to be obtained since the modulation index M could be made very close to its optimum value of one. This was desirable since the fundamental component would decrease and the carrier frequency amplitude would increase as the modulation index was made less than one thus requiring a progressively larger output filter. In order to build a transformerless inverter, the input voltage to the power stages must be bi-polar and be high enough to produce the required three- phases output voltages specified in the Methodology plan. Therefore, a DC - DC converter was required to provide these voltage requirements from the source. A detailed theoretical design for the 400 cps - 10 KW PWM inverter was under- taken to obtain tentative circuits and parts lists in preparation for the bread- boarding phase. In addition, typical values of efficiency, weight and reliability were obtained from this theoretical design. A conceptual circuit design was obtained for the 400 cps - 10 KW PWM inverter which was considered as representative of the actual circuitry that would be needed since much bread- boarding of the individual circuitry would be required in order to finalize the design. This circuit design contained a three phase square wave reference generator that produced the low frequency (400 cps) modulating signals which were square waves displaced lZ0 degrees apart. The reference signals were pas sed through controllable attenuators which had a normal attenuation of zero. These attenuators were used for overcurrent protection by attenuating the size of the modulating signal which in turn reduced the voltage of the overloaded line. The fundamental frequency of the output square wave from the attenuators was extracted by tuned amplifiers which had unity voltage gain at 400 cps. The 400 cps sine waves produced by these tuned amplifiers were then mixed with the sweep wave in the three summing networks. The sweep wave was a generator which produced a sawtooth sweep wave at the carrier frequency. The resulting waveform that came out of these summing networks was a sinusoidally modulated sawtooth wave which was sent to the slicer circuits. The slicer circuits sensed the absolute level of these waveforms, thus pro- ducing pulses which had their widths proportional to the modulating signal level during the sampling interval. The variable pulse width signals were then amplified and sent to the driver stages which transformed these signals into a form suitable for use by the power stages. The power stages converted the low level drive signals into the required high power levels. The high voltages required for the power stage was supplied by a DC - DC converter from the low voltage source. The DC - DC converter was also used as a voltage Z8 regulator to maintain the voltage across the power stages constant. The output filters were used to extract the carrier and its sidebands from the output voltage leaving only the power frequency voltage. Both the power stage and DC - DC converter were given special design attention since they were the circuits that were required to control this high power. The power stage contained six half phases which were required for a transformerless output. Each half phase contained a number of transistor switch legs that were connected in parallel to handle the required load current. The number of these switch legs would be determined by the current capacity of the individual transistors selected. The maximum voltage across the half phases was found to be 380 volts for a 115 V rrns output. This was rather a high voltage, making it difficult to find a transistor that had both high voltage and current ratings along with very high switching speeds. An RCA develop- mental type TA2110 transistor with a VCE X of 400 volts and 10 amp current capacity was found that had very fast switching speeds. However, its voltage rating only provided a 5% safety factor which was below the minimum design goal of 200%. This design goal could be satisfied by connecting two of these transistors in series producing a safety factor of 211%. Voltage divider resistors were required to equally divide the supply voltage across the power transistors connected in series when they were in the "oil _ condition since their collector leakage currents could be unequal. These resistors were connected in parallel with each transistor. The maximum switch current that each half phase must be able to supply could be as high as 250 percent of rated current at . 7 P.F. or a maximum current of 147 amps. Since the RCA developmental TA2110 was rated for I0 amps, a total of fifteen of these transistors must be connected in parallel for each half phase. Thus, the series-parallel transistor combination netted a total of 30 transistors per half phase or a total of 180 transistors for the power stages. Because the saturation voltage could vary for the switching transistors, some sort of current balancing technique will be required. This balancing technique must b_ simple and have a high efficiency. Two non-dissipative current balancing techniques, one using split transformers and the other using balancing _ reactors, were examined in detail. The results of this study indicated that balancing reactors connected in a closed chain for each half phase would be the lightest and most efficient approach to balance the transistor load currents for this nominal D.C. voltage of _200 VDC. The balancing reactors must be designed to support the maximum voltage unbalance that could exist between the saturated transistors. Blocking diodes were connected in series with each half phase to prevent reverse current from flowing through the power transistors. The blocking diodes must have a very fast recovery time to. reduce its switching losses when the switch legs were being cornmutated "on" and "off". Reactive diodes 29 must also be connected across the input to each half phase to provide a current path for the reactive current when the blocking diodes were in the circ uit. The power stage weight and efficiency were found. The power stage weight was 55. 239 pounds for 1059 parts while the full load power stage efficiency at . 7 P.F. was calculated to be 89.14%. The DC - DC converter was used to provide a regulated bi-polar high voltage to the power stages from the unregulated low voltage source. TheDC -DC converter must be capable of supplying the 250% overload capacity to these power stages. A number of converter techniques were investigated with the result that a pure square wave system with pulse width modulated riders was selected. The output filter for this converter was very small since pure square waves were being rectified and the switching stage used to control the DC input to this stage had only to handle the power required to raise the source voltage up to its maximum level. Therefore, at the high source voltages, the switch handles no power, while the maximum power it controls was at the low source voltages. This means that the transformer used in the switching section could be smaller for the voltage stepup system. Both of these factors contributed to a lower overall system weight. A tentative operating frequency of 1000 cps was selected to provide an optimum design between efficiency and weight for this converter. The slow switching speeds of the 150 amp power transistor and hence their switching loss was the major deterrent in going to higher operating frequencies. TheDC - DC converter weight could be reduced substantially while still retaining its high operating efficiency if higher oper- ating frequencies could be used if and when 150 amp transistors with higher switching speeds become available. The DC - DC converter weight and efficiency could now be found. The con- verter weight was 50.3 pounds while the full load efficiency at . 7 P.F. was calculated to be 91.4%. A reliability study was performed on the electrical circuitry and their parts for the proposed 400 cps - l0 KW PWM static inverter. This reliability study could only be used as a guide since the circuitry was created from a theoretical. design and the stress levels assigned to each component were based on this theoretical design with no actual stress measurements being taken. Packaging techniques and electrical connections were not included in this reliability study. The parts failure rate approach was used to analyze each component that would represent the overall circuit configuration. Each major circuit was represented by one of these blocks. Sub-blocks were assigned to each major block to represent the individual circuits or components that were required to create a major circuit. An overall Reliability Figure of Merit R could be found for this 400 cps - 10 KW PWM Static Inverter from the 30 representative circuits for each sub-block in the reliability block diagram. Examining the block diagram revealed no redundant circuitry was used in the low level logic, DC-DC converter, and the pre-driver stages. However, the power output stages can contain redundant circuitry depending on the mode of failure and the permissible maximum current allowed. Power transistors usually fail in the shorted mode of operation. Thus, a maximum of one transistor in each switch leg or a total of 15 transistors, one in each switch leg for each half phase, could fail in the shorted mode without degradation of the output waveforms. The voltage safety factor across the unshorted,trans- istors, however, was reduced from Zll% to 5%. A catastrophic failure would occur if both transistors that were connected in series in one switch leg should fail in a shorted mode causing the loss of a half phase. The use of fuses in each switch leg would prevent this catastrophic failure by clearing the shorted switch leg. However, the current capacity of the half phase would be reduced, If the power transistors should fail in an open mode, then a maximum of nine switch legs would be lost per half phase with the inverter load capacity being reduced from 250% to 100% of full load. The same generic failure rates, derating factors and environmental operating modes used for the electrical components for the 3Z00 cps - l0 KW reliability analysis were used here. The operating time for each component was determined. The reliability figure of Merit R was then determined from this information for the three possible modes of failure in the power stages. Again, a Z0-mtnute missile launch combined with one month and then one year continuous operation was used. The results of this study indicated that the lowest reliability figure of merit for one year (R = . 498Z63} was obtained for the catastrophic failure of two power transistors in the same switch leg without fuse protection. The highest reliability figure of merit for one year (R = . 80865Z} was obtained for the failure in the open mode of nine switch legs per half phase. These relia- bility figures of merit could be improved especially in the DC-DC converter circuitry and low level logic by the use of redundant circuitry. The reliability of the power stages could be improved by using more redundant switch legs. A detailed design study had been completed for the 400 cps - 10 KW static inverter using classical pulse width modulation and natural sampling. A conceptual design was created using the Methodology plan as a design guide. Complete electrical circuits and their parts lists, and all reliability numbers, weights, and losses were based on this theoretical design and should only be used as a guide for this conceptual design. Improvements in efficiency, weight, and reliability should be realized if this conceptual design is fabricated and tested. Assuming that the 400 cps - l0 KW static inverter design is performing to the Methodology plan, a detailed reliability analysis may be conducted in which the electrical and thermal stresses of each circuit component are care- fully measured. The overall reliability can then be computed with a high degree of confidence. Reliability recommendations may be incorporated into 31 the circuitry wherever possible to improve the inverter's reliability figure of merit. Intangible items such as heat sinks, connectors, terminal boards, fuses, etc., in the theoretical design may now be accurately determined in the breadboard phase so that a final package configuration can be established. Shock, vibration, and other environmental conditions will also be considered for this final package design. The present conceptual design does not use a bulky power output transformer• The elimination of the power output transformer allows the power output stages to be readily adaptable to modular construction. Therefore, each switch leg in each half phase can be constructed as a simple module that can be easily replaced. The modular construction techniques allow these power output stages to be easily scaled to any power capacity by adding or removing switch leg modules which are connected in parallel for each half phase. For example, the present 10 KW inverter with a Z50% overload capacity can be reduced to a 4 KW inverter with a 250% overload capacity with the removal of nine of these switch leg modules per half phase• The driver stages, output filter components, DC-DC converter, and current feedback circuitry will also require modifica- tions in order to be compatible with the power output stages. Modular con- struction will be used in these circuits where possible to simplify these modifications. At present, the conceptual design offers a lightweight (147• 54 lbs. total com- ponent weight) and a fairly high efficient (80• 4% overall at full load and • 7 P. F. ) inverter. However, its overall reliability figure of merit will have to be improved considerably either through the use of redundant circuitry or with less complex circuit designs. A minimum safety factor margin of two was used for a design goal in this theoretical design wherever possible. Circuits which employ components that cannot meet this design goal will be thoroughly investigated in order to determine alternate approaches that can be used. Thus, the use of two power transistors in series per switch leg can be eliminated if an equivalent transistor with an 800 VCE voltage rating could be found. This would eliminate divider resistor losses (144 watts) and cut the base driver power requirements in half (save Z70 watts) making a more efficient inverter. Therefore, the conceptual design will require more design considerations together with extensive breadboard testing of the individual circuitry before an optimum 400 cps - 10 KW static inverter design can be realized whose electrical parameters will either comply with or exceed those defined in the Methodology plan. 3Z BODY OF REPORT GENERAL INFORMATION I. DESCRIPTION OF INVERTER TYPES A. Introduction Solid state inverters are designed almost exclusively around two types of switching elements: silicon controlled rectifiers (SCRlsi and transistors. The difference between these, of course, is the lack of ability to turn off the SCR at the gate; an external means must be provided to reduce the current in the SCR to zero. Provision must be made for this in all circuits using SCI_ I s. In some circuits, this turn- off is an inherent part of the circuit; in others it is inherent for some load ranges, while in still others extra components must be added to provide this turn off. Series type inverter circuits which are used almost exclusively with SCR's are of the first two types. Their permissible load change, however, is limited to approximately 3 to 1. Parallel inverters (which are used with both SCRts and transistors) generally belong to the last class. B. Parallel Inverters a) Simple Parallel Inverter The basic parallel circuit is shown in Figure 4-1. Here the switching elements are shown as switches, since both transistors and SCRWs are used in this circuit, For use with SCRIs the components shown dotted must be included to provide for proper commutation of the SCR's. The transistorized circuit puts out a square wave voltage into a resistive load; the output voltage of the SCR inverter, because of the resonant effects of L and C is a complex function of the value of L, C, the operating frequency, and the load. For the graphical presentation of the results of a steady state analysis of this type of inverter, the reader _s referred to the literature "Parallel Inverte_ with Resistive Load"-, and "Parallel Inverter with Inductive Load" 7 4 "Parallel Inverter with Resistive Load", C.F. Wagner, A.I.E.E. Transactions, V54, November, 1935, pp. 1227-1235. "Parallel Inverter with Inductive Load", C. F. Wagner, A.I.E.E. Transactions, V55, September, 1936, pp. 970-980. 33 Unfortunately, these papers do not investigate the operation of the inverter under unloaded or switched conditions. It can be shown as follows that this inverter will not operate under no load conditions. Consider any one half cycle of inverter operation. The equivalent circuit of Figure 4-1, under no load conditions, is shown in Figure 4-2. If we assume that the SCl%ts are alternately gated on at a frequency w lower than the resonant frequency of the cornmu- o = 1 tating components w c 4_> w o then, at the time of the closing of S, there is no current in-the circuit. When S is closed, the _ following differential equation applies to this circuit: -(- LT - + t-C -- :o- L This has the solution: (4 - I " (E +FUI_oi sin 2 The solution, however, is only valid for i_ 0, since S only conducts in one direction. Thus, this solution is valid only for 0--< t_ 2ST_--C-. During this time, the capacitor voltage changes from _ to . "-- --_'_ --2_ E . Thus, in each half cycle, the equivalent capacitor (4Ci voltage increases by 2E, or the voltage on the actual capacitor C c increases by 2 (2E i - 4E. Therefore, either the output transformer will soon saturate from the overvoltage or one of the SCI%Is will conduct, in either case resulting in a double fire or latch-up condition where both SCR's are conducting simultaneously. This is indicated in the waveform drawing of Figure 4-3, where the voltages are shown building up from the starting condition of v o - 0. For very light loads, a similar situation occurs at start, except an equilibrium condition may eventually be reached if the voltage ratings of all the components are high enough. To handle inductive loads, the commutation capacitance C c must be large enough to absorb the reflected load current for that part of the cycle during which the load is returning energy to the inverter (i.e. the load voltageand current are of opposite signi without having the capacitor voltage rise to a destructively high value. This is also discussed in the literature previously cited in "Parallel Inverter with Inductive Load". 5 5op. cit. 34 For an inverter which must operate over a wide range of (lagging i power factors, this can result in a considerable excess of commutation capacity at normal or light loads, giving rise to a condition similar to the no load case described. Thus, this type of inverter is not suited for general purpose applications where the load is of variable magnitude and. power factor. This inverter, like all SCR parallel inverters also will not operate if the load impedance becomes too small. A detailed discussion of the reasons for this limitation in the case of the McMurray-Bedford circuit is found in Appendix 4-I! the same reasoning can be applied to this configuration. Depending on the values of L, C_ load, and operating frequency, an SCR which has been conducting may either be turned off by the attempt of the current in it to reverse its direction, or by the action of the cornmutating capacitor in pulling the anode voltage of one SCR negative when the other SCR is first turned on. bi The McMurray-Bedford Parallel Inverter improved operation of this circuit can be realized by the addition of so-called "reactive" diodes to provide a path for reactive currents which formerly went into the commutating capacitor (for the SCR ctrcuit)o This allows operation for all load power factors. The reactive diodes also serve to limit the voltages under no-load conditions, (the capacitor voltage is held to 2E i so that operation under no-load is now possible. The new circuit is shown in Figure 4-4; again, the additional parts required for an SCI_ inverter over a transistor inverter are shown. A detailed analysis of the operation of the SCR parallel inverter with reactive diode_ (the McMurray-Bedford clrcult) is given inAppendix 4-I. Waveforms of the SCK inverter at startup and steady state are given in Figures 4-I- 11 and 4-I- 12. C c is chosen according to Equation 4-I-15 to provide the desired minimum turn-off-time (e° g. 20 usec) for the SCR's under the worst condition of commutating the maximum current at the minimum capacitor voltage. L C is generally chosen to resonate with C C at a frequency with half period approximately twice the turn-off-time. This is only a guide and L C may be varied as desired, keeping in mind the following effects: For a constant CC, source voltage, and current to be comrnutated: I) As L is decreased, the available turn-off time is decreased because the commutating capacitor can be discharged more rapidly, l_efer to Equation 4-I-29. 35 As L is decreased, the peak charging current to the capacitor is increased (Equation 4-I-2i although the average value (which determines the energy delivered to the capacitor i remains approxi- mately constant; thus, the rms value of the current is increased, resulting in increased i2R losses in the choke and output trans- former. 3)As L is increased, the circuit is more affected by suddenly changing loads. A sudden increase in load currents results in a voltage developed across L in such a direction as to cause the commutatlng capacitor C C to partially discharge into the load. If L is too large, this effect can cause circuit failure upon load switching. Because of the action of the reactive diodes in providing a path for reactive currents and limiting the capacitor voltage under light loading, this circuit will operate and start under a wide range of load magnitudes and power factors; however, should the load become too heavy, resulting in excessive currents at the time of commutation, then according to Equation 4-I-15, the circuit provided turn-off time is decreased and the inverter malfunctions. ci Gate-Controlled Switch P_rallel Inverter Idealized waveforms for a transistorized or gate controlled switch (GCSi parallel inverter operating with a resistive load are shown in Figure 4-5. These are much less complex than those of the SCK inverter as shown in Figure 4-I-11 because of the absence of the commutating choke and capacitor from the circuit of Figure 4-5. Table 4-I compares the various types of SCR inverters with respect to several parameters such as weight, efficiency, etc. These ratings are based on 400 cps inverters with 5% total harmonic distortion and operating at the 1 KW level. This table shows that, in general, for fixed load operation, the series inverter is superior, but for large load variations, the McMurray circuit is favored. If. VOLTAGE REGULATION The output voltage of all the inverters mentioned previously was a direct function of the D.C. input voltage and could be varied by changing this voltage. A series or phase shift A.C. output regulator or a D.C. voltage regulator may be used to regulate the output voltage of these Inverters. These regulators are controlled by an error signal that is developed by comparing the A.C. output voltage with a reference to provide a closed loop control of the inverter output voltage. The following discussion will deal in detail only with the D.C. voltage regulators. 36 A. Series Proportional D.C, Regulator The simplest type of d.c. regulator (and the lightest, if heat sink requirements are not considered) is the series regulator, shown schematically in Figure 4-6 and equlvalently in Figure 4-7. For a load current I, the power input to the regulator (neglecting the power required by the low level control and sensing circuits) is VI, and the power output of the regulator is V I. Thus, the maximum efficiency is o . p_o_o. Vo__L. vo. Pi VI V Thus, for greatest efficiency, the output voltage sholtld be as close as possible to the input. However, the regulated output can never be greater than the least value of the input; therefore, for any but sma]_l variations in voltage, this regulator becomes rather inefficient. Furthermore, the power lost in the regulator, (V - V i I, is all dissipated in the series control element which must t_en be adequately heat-sinked. B. Series Switching DpCt l%egvAator One of the first switching type d.c. regulator circuits used the same series tramsistor as the simple series regulator, but turned it full on or full off depending on how the output voltage compared with a reference° A simple LC filter smoothed out the large voltage variations caused by this switching, and a flyback diode was added to provide a path for the choke current during the periods when the series switch was oH. The resulting circuit is shown in Figure 4-8, and the waveforms in such a circuit in Figure 4-9. The losses in this circuit are less than those of Figure 4-6, for most cases and can be analyzed as follows: Assuming a switching period of_ and a choke large enough so the current is approximately constant, the "on" time t 1 is approximately related to the period and the input and output voltages by the equation V - tl -- Vin (4-2) o 3- Therefore for a load current Io, the losses in the circuit will be: 1. Io2 R L in the series choke 2° Io V S tl in the series switch 3. I0 VD _-_ _in "the flyback diode 3- 37 where V D is the forward drop across the flyback diode, V S is the forward drop across the series switching element and RL_S the resistance of the filter choke. It can be seen that these losses are independent of the input and output voltages. This is strictly true only for the case where V S - VD; otherwise the losses will vary slightly as the ratio of input to output voltage changes, because the thne ratios tl/- _- and _ will vary as this ratio changes. Thus, this circuit is suitable _in applications where the input and output voltage of the regulator may differ by large amounts. Because of the choke, it is heavier (for a given currenti than the circuit of Figure 4-6, but this difference can be minimized by performing the switching at as high a frequency as possible (consistent with transistor switching lossesi to reduce the choke size. Since this is a switching type regulator, it is also possible to use SCK's or GCS's in place of the transistor. With SCR's the circuits become more complex, again because of the necessity of having some method for turning the SCR off. A typical circuit (the Morgan Chopper) and its waveforms are shown inFIgures 4-10 and 4-11. The operation of this circuit is discussed in the literature. 6 Both the transistor and SCR series type switching regulators provide an output voltage which can be no greater than the input. C. Shunt Switching D.C. l%e_ulator (Bedford Step-up Circuit i The newly developed Bedford circuit shown in Figure 4-12 removes 7 this restriction by providing an output not less than the input voltage. It operates in the following manner: (refer to Figure 4-12 and the waveform Drawing 4-13i. Transistor Sperforms the same function as a single pole - single throw switch. When transistor S is turned on (saturated} the only current path provided for the source is through the inductor L and the saturated transistor S, thus making I i = Is. During this time the current through the inductor is building up. When the transistor S is turned off (unsaturatedi, the current Is through this transistor drops to zero. However, the charging current Ii through the inductor L is maintained by flowing through diode D into capacitor C and the load. Capacitor C is charged up causing a decay in the inductor current (because the output voltage becomes greater than the input voltagei until the transistor S turns on again. Diode D is used "Silicon Controlled Kectifier M.anual", General Electric Company, p. 149-151. "Q_arterly Progress Report lqo. 4 on Voltage Regulation and Power Stability in Unconventional Electrical Generator Systems" (ASTLA #AD265158), p. 87. 38 to isolate the capacitor C and load from the charging circuit composed of indicator L and transistor S thus preventing the capacitor from being discharged through transistor S when it is turned on. While transistor S is turned on and current is building up in L, the load current is supplied entirely by capacitor C° With an input of V i volts and Ii amps, and an output ofV o volts (V O_Vi) and I amps (I /_I_) the average current carried by the switching elementUls Ii - Io° the average current carried by the diode is Io. Assuming an inductor resistance of RL, diode drop of V D and switching element drop of VS, the losses in this circuit are then Ii 2 I%L+ (li_ioiV S +loV D. Again, this is independent of the input and output voltage to the same degree as the losses of the series switching inverter. Figure 4-13 shows the waveforms in the Bedford circuit for a step-up ratio of 2: 1. D. Inverter-Rectifier D. C, P_eA_u/ators Other circuits for d.c. regulation involve changing the d. c. to square wave a. c° with a simple parallel inverter, and then operating on this a.c. with various types of modulators and rectifiers. Though more complex than the previous techniques described, this method is of advantage where the raw d. ¢. input is not near a value that can be readily used by the inverter; any desired amount of step-up or step- down in voltage can be obtained with this technique by simply varying the turns-ratio of the inverter transformer. Since this incorporates inverter stages, which will be d_scussed in great detail later, and furthermore could not be advantageously used to provide a more optimum d.c. voltage level to drive an inverter (since it itself is an inverter and w_uld have to work at the least optimum voltagei, this method will not be discussed further. E° Buck Boost D_ C, Regulators A modification of the above technique is theuse of a square wave inverter-modulator-rectifier to provide only the difference voltage between the raw d° c. inpttt and desired d° c° output. Its output is then connected in series with the d.c. input to provide the regulated output. The advantage of this system is that the inverter-modulator is required to pass only the error power instead of the total d. c. load. The output rectifiers still pass the full load current, however, so the losses here are not decreased. The circuitry used in this technique is shown in Figure 4-14. This circuit can be designed to subtract from as well as add to the raw d.c. input voltage; if this is done, the maximum error power required is reduced by a factor of 39 two, since the maximum output voltage of the regulator can be halved when its output can assume either polarity. F. Quasi-Square Wave Regulation Techniques a) Quasi-Square Wave Power Stage Another method for voltage regulation involves increasing the complexity of the basic inverter circuit to provide for changing the output waveform of the inverter as required. One of the simplest outputs resulting from this is called a quasi-square wave and is illustrated in Fignre 4- 15. Harmonic analysis of the resultant wave (shown in Figure 4-15) indicates the variation of the fundamental component of this wave with the dwei1 angle (_. v(t) - 4V _sin wt cos (_ + 1/3 sin 3 wt cos 3 (_ +TTI_ sin 5 wt cos 5 (_ + I sin (2m-l) wt cos (Zm-l) (_J 2m-1 (4-3) Where the harmonic number (Rm-l) is determined by m which ranges from one (I) to infinity ( Z>O ). (m=l, Z, 3, 4 .... EO). Hence, by changing (_, the peak amplitude of the fundamental component of the above wave can be varied between __4V and 0. -rr With transistors and a resistive load, this can be easily accom- plished by only turning them on when an output is desired, instead of always having one on. This is indicated in the waveform drawings of Figure 4-5. When using SCR's the problem is more complex, since in all the circuits for parallel inverters discussed so far, the only way one sen is turned off is to turn the other one on. Hence, in SCR inverters, additional circuitry is required to produce the output waveforms of Figure 4-5. III HARMONIC REDUCTION In general, the harmonic distortion of the unfiltered output of these switching circuits is too high for many applications. Two obvious solutions are to either filter the output to remove the undesired harmonics or to use circuits which produce less harmonics. The optimum design is usually a combination of these two, since it is not too difficult to construct an inverter that suppresses the lower harmonics in the switching stages, and the higher ones are readily attenuated by simple filters. A. Single Step Waveforms (Quasi-Square Wave) The simple quasi-square wave, with (_ =30" has no third harmonic; 4O three such waves each displaced by 120", can be generated in a simple 3 phase bridge circuit as shown in Figure 4-16. This can provide a good start for a three phase inverter; however, holding (_ at 30" (or any other fixed value) means giving up the voltage regnlation capability of the quasi-square wave. Thus, some additional means is required for voltage regulation in situations where (_ is held fixed for harmonic reduction purposes. B. Multi-Stepped (ht_ts Another method for reducing the distortion produced by the switching stage is to use a more complicated switching arrangement which is capable of providing intermediate values of output. Such a circuit is shown in Figure 4-17. Here the switches (either transistors or SCR's may be used) are closed in the proper sequence to provide the stepped waveform also shown in Figure 4-17. In this scheme, the switches farthest from the center tap provide the lowest output voltage, etc. Providing for reactive current in a scheme such as this can be a problem unless certain switches can be made bi-directional. It is also possible to produce such a waveform by adding a number of square waves of proper phase relationship in a technique which is an extension of that shown in Figure 4-18. These more advanced switching techniques become more advantageous in multiphase inverters because several gating signals will be common to two phases; the control section for a three-phase multlstepped inverter cannot be appreciably more complex than that for a single phase unit. Voltage regulation in these more complex techniques may be obtained by a d, c. input regulator, by varying the width of some step in the waveforrn, or by adding together two such waveforms with a variable phase difference. C. Constant Voltage Transformer Techniques A combination of voltage regulation and harmonic suppression can be obtained through the use of special ferro-resonant transformers designed for this purpose (e. g. the Sola transformer). These, however, have fairly high no-load losses and an output voltage somewhat sensitive to load power factor. They afford a very simple and reliable means of voltage regulation and harmonic suppression and also provide short circuit protection. When starting unloaded or operating under switched loads, they sometimes draw large spikes of magnetizing current, successful operation of an SCR inverter power stage under these conditions required a large commutation capacity when compared to normal demands. 41 D. Static Tap Changing One technique of voltage regulation which can be useful under certain conditions is static tap changing. As shown in the diagram of Figure 4-19, this uses semiconductors acting as switches S 1, S2 .... to connect one of several possible taps on the output transformer to the load. Two representative techniques for utilizing SCK's and transistors in a.c. (bidirecttonali static switches are shown in Figure 4-20. Which tap is selected will depend on the load and input voltage to the transformer. This technique has the advantage that it allows voltage regulation of a complex mu/tistepped waveform with- out introducing distortion or phase shift as would be the case with a conventional on-off output modulator. This would be especially useful in a situation where the input voltage was very low so that an additional semiconductor in series with the input side (as would be the case with a conventional d.c. input regulatori would result in excessive losses, but where the output voltage of the switching stage transformer was high enough so that the drop in the static tap changing switching elements would represent a negligible fraction of the output power. The disadvantage is the large number of taps, and hence semiconductors required when either the d.c. input voltage to the power switching stage varies over a wide range (compared to the permissible variation in outputi or the output voltage tolerance is so stringent that variations in output due to changes in load require a large number of taps. E. High Frequency Techniques SCl%'s could also be used to modulate a high frequency square wave to obtain a pulse-width modulated output like that of Figure 4-21. A block diagram of such a system is shown in Figure 4-22. Other techniques for low order harmonic reduction are the various types of pulse modulation. The switched output and fundamental component of such a circuit is shown in Figure 4-21. These waveforms would be generated by circuits similar to those already discussed for square waves| the only difference being that the circuit is switched several thnes in each cycle. In these circuits, switching losses become much more significant, and components designed especially for high frequency use become a necessity. Figure 4-23 corresponds to a high frequency version of the qtmsi-square wave and can be generated by circuits similar to those used for the usual quasi-square waves. The advantage of the waveform of Figure 4-21 over that of Figure 4-23 is discussed further in a following section (Section II-A, B, of 400 cps - 10 KW P.W. IV[. Inverter Designi. 42 The advantages of these high frequency techniques lie in the size and weight reductions possible both from high frequency operation and from _he fact that the harmonics present in the unfiltered output are of a very high frequency compared to the fundamental, simplifying filtering. The main disadvantage is the increased switching loss. There is also presently a rather limited selection of semiconductors in the high power high frequency field. It might also be mentioned that unlike inverters of the quasi-square wave plus brute force band- pass filter design, which are restricted to sine-wave outputs, pulse width modulation inverters, which can efficiently use low-pass filters, are capable of providing any desired waveforms with highest frequency harmonic below the cut-off of the particular filter used. F. Passive Filters Filters used for the outputs of the simpler inverter circuits generally consist of a series element (which is generally series resonant at the fundamental frequency i and a shunt path (which is capacitive at high frequencies and may be tuned to parallel resonance at the fundamental frequency i. The series section may also have impedance poles at those frequencies of greatest harmonic magnitude. The shunt section may likewise have impedance zeroes at appropriate harmonics. The basic filter concept is shown in Figure 4-24. In general, it is desirable to have the series element provide a low impedance path for the fundamental and a high impedance to harmonics. This first allows the fundamental current to pass without voltage drop from the inverter switching stage to the load, while the high harmonic impedance prevents harmonic currents from flowing in switching stages, thus reducing dissipation. Similarly, the shunt path ideally presents an open circuit to the fundamental and a nearly short circuit to harmonic currents. (These harmonic currents may be the small amount that get through the series filter section, along with any due to load non-linearily.i As mentioned previously, pulse width modu- lation filters can be of the low pass type since the pulse width modulation waveform is essentially free of the lower order harmonics. One proposed method for harmonic reduction in polyphase systems involves the use of a distributed transformer to couple the switching stage to the load. This can best be described as a wound rotor induction motor with locked rotor and having fractional pitch windings and skew selected to eliminate specified harmonics. G. Active Filters Another method of harmonic reduction is the use of active filtering. This involves using an error amplifier to make up the difference 43 between the swltch_ng stage output and the desired sine wave output as provided by a sine wave reference source. A block diagram of such a system is shown in l_isure 4-25. 44 3200 CPS - I0 KW INVERTER DESIGN I. INT RODU CT ION Two basic power inverter approaches were considered for this 3200 cps - 10 KW Inverter Design. The first approach utilized the Pulse Width Modulation techniques while the second approach employed the Multi- Stepped Waveform techniques. The Pulse Width Modulation approach was found to produce excessive switching losses when operating at the power frequency of 3200 cps. This resulted because switching devices with reasonable current capacities could not be found with the necessary switching speeds (t s < . I us) to minimize these switching losses when switching at the minimum modulating frequency of 16, 000 cps. Therefore, the Multi-Stepped Waveforrn approach was chosen for this 3200 cps - 10 KW inverter design. A preliminary comparison between two I0 KW - 3200 cps inverters, one using SCIUs and the other using transistors was made on the basis of the calculated weights, efficiencies, and parts count. The results indicate that although the SCR inverter has only half the parts count as the transistor inverter, its efficiency is less (64% versus 70°/0j and its parts weight is higher (62.25 lbs versus 50 lbs) than its transistor counterpart. (_kbles 4-2 and 4-3 are used to compare efficiency, weight, and parts count of both inverters, j Because of the higher efficiency and lower parts weight offered by the transistor inverter, the circuit design was concentrated on the multi-stepped transistorlzed output inverter approach. The following sections are used to establish this 3200 cps - 10 KW Inverter Design, H. STEPPED WAVEFORMS The basic requirements of Stepped Waveforms on the reduction of Harmonic Distortion outlined in Section III-B (Alulti-Stepped Outputs) are examined in more detail in this section. A variety of stepped wave- form characteristics that have been proposed by contributors to the field of static inverters were investigated in an effort to reduce the size of the filter requirements for an allowable harmonic distortion level and yet maintain complexity of the inverter circuitry to a minimum. The waveforms evaluated here are classified first as to the number of horizontal steps that can be counted in a full cycle. Therefore, a wave can be classified simply as an "eight" step or a "six" step waveform merely by counting the steps. Further subclassification is then made by determining if the steps occur at equal or unequal time intervals and are called either equal time or unequal time waveforms respectively. The next subclasslfication made is whether the step heights are equal or not 45 equal in amplitude and are called equal height or unequal height wave- forms respectively. We now have a system that can classify any stepped waveform that is used to synthesize a sine wave. Table 4-4 lists the waveforms that will be evaluated here. The numbers in the second column signify the number of steps in the waveform. The stepped waves examined here can be broadly classified into two groups for discussion. The first group are waveforms (phase voltagesi that can be divided by the smallest time increment step into an integral even number of parts. (Refer to Figures 4-26 through 4-40.) These waveforms have steps of uniquely optimum height, as some authors put it, that specifically reduce the number of lower harmonics and the harmonics that appear do so at predictable points. Several authors 8, 9 have come upon this relationship which can be made applicable to wave- forms fitting this description. The relationship is that harmonics only appear in pairs according to the equation h = Nnel (4-4) where h is the harmonic number, N is the integer arrived at by dividing the waveform by the smallest time increment step and n is any integer from 1 to infinity. This test can be applied to thewaveforms numbered i, 2, 3, 5, 6, 7, 9, Ii, 12, 14 and 15 il/ustrated in Figures 4-26 to 4-40. A proof of the validity of this relation can be made by selecting a wave- form and expressing it as a Fourier series and then examining the harmonics. Waveform 6-P will be used as an example (refer to Figure 4-31i. The waveform is described as a six step-unequal time-u_equal height waveform. However, by dividing the waveform by the smallest time increment between steps (45"i, the integer eight is obtained which fits the basic requirement previously stated. The harmonic numbers are then: h = 8n'±l (4-5) 9 ,,Methods For Optimizing the Waveform of Stepped - Wave Static Inverters", P.D. Corey, A.I.E.E. Paper No. CP-62-I147. "Static Power Inverter Utilizing Digital Techniques and Harmonic Cancellation", D. L. Anderson, A. E. Willis, C. E. Winkler, A.I.E.E. Paper No. CP-62-I148. 46 according to this equation the only harmonics will be n -- I, h - 7, 9 n - 2p h - 15, 17 n - 3, h ,, 23, 25 n - n, h - 8n± I This can be proved by examining the Fourier series expansion of the waveform which is: e " "IT4---V_I+__ cos45"}slnwt+1/3(I+_cos135")sin3wt +1/5(1+ osns"is I/7(I+ cos315"i + 1/9(1+/_ cos45 ° islngwt+ 1/I 1(I+_ cos135 ° isinll wt + 1/13(1 +5 cos225" ) sinl 3wt+ 1/15(1 +J2"cos 315 ° }sinl 5wt + 1/17 (1+/2 cos45" islnl 7wt+ 1/19 (1+J2--cos 135" )sin19v_ 1 /21 (1_/+2/2--cos225° )sin21wt+ 1/23(1 +_-cos 315"+ )s 3wt + 1/25 (1 +_- co s45" )sin25wt+. 45" i s in(2n- 1 }wt_ "" + (2n-1i (l+_cos (2n- 1} (4-6i By examining the harmonic coefficients it can be seen that the third_ fifth, eleventh, thirteenth, nineteenth, and twenty-first are equal to zero. The only harmonics present are the seventh, ninth, fifteenth, seventeenth, twenty-thlrd, twenty-flftlN and the (8 nel)th as predicted by the relation- ship. The magnitude of the harmonic can also be derived by inspection as (1/hi times the magnitude of the fundamental. The second group of stepped waveforms are those which have been specifically designed to have either the minimum total harmonic distortion possible for a waveform having a particular number of steps, or designed specifically to eliminate certain harmonics. Waveforms fitting this description are shown in Figures 4-29, 4-33, 4-35, and 4-38. 10 Figures 4-29, 4-35 and 4"38 were derived by Mr. Paul Vergez of Texas Instruments. Mr. Vergez used a digital computer to determine the proper i0 "Electronic Design", April 26, 1964' pp. 36-42 by Paul Vergez. 47 time increments and step heights that yield the waveform with the minimum total harmonic distortion for a particular number of steps. Figures 4-29, 4-35 and 4-38 shown in this report have been normalized to conform with the method established for constructing waveforms, namely the first step is of unit height V. Figure 4-33 is also in the second group and has been specifically designed to eliminate the third and fifth harmonics and all multLples of the third and fLfth harmonics. This characteristic is evident by examining the Fourier series expansion of the waveform which is: e ffi _ cos 12" + cos48" istnwt+ 1 / 3(cos 36° + cos 144° }s fn3wt+ 1/5(cos60° + cos240" i sin5wt+ 1 / 7(cos84" + co s 336" isin7wt+ "'" ÷(2n-li (c°s(2n- iil2" + c°s (2n- 1i48° isin(2n- ii (4-7i From the expansion it can be seen that the coefficients of the third and fifth harmonics are zero (cos 36" = -cos 144" and cos 60" - -cos 240"i. The multiples of the third and fifth harmonic are also equal to zero; and cos n 36 e '= COS n 60 ° ffi -cos n 144" -cos n 240" The application of the stepped waveforms to static inverters demands certain characteristics of the waveform for three phase operation. The waveforms discussed in this report have their characteristics tabulated in Table 4-4 and the item of interest here are the columns listing the number of square wave Lnverters required to generate a single phase voltage and a three phase voltage. In some of the waveforms, a single square wave inverter may supply two or even three phases with a required step and therefore be a more optimum choice. Waveforms requiring no increase in the number of basic square wave inverters to generate three phases compared to the number required by a single phase are obviously the most optimum choices. Waveforms having this desirable characteristic are shown in Figures 4-30, 4-37, and 4-40. Waveforms which are complementary to Figures 4-37 and 4-40 are shown in Figures 4-36 and 4-39 respectively. In these waveforms, the number of inverters required to generate a three phase voltage are the same as those in Figures 4-37 and 4-40, but one less square wave is required to generate a phase voltage. This feature fs an advantage in single phase inverters but of no particular advantage in a three phase inverter because 48 the phase loads are less equally distributed among the square wave Inverters. Figure 4-33 is the next most optimum waveform ,based on the criteria established above. For use in a three phase inverter, no other feature of this waveform appears to be any advantage except perhaps the fact that all the secondary windings required to generate the waveforrn are equal. The only other wave.forms useful for three phase inverters based on the criteria are illustrated in Figures 4-28 and 4-30 which are complementary. The other waveforms (Figures 4-26, 4-27, 4-29, 4-31, 4-32, 4-34, 4-35, and 4-38) are totally unsuitable for three phase inverters based on the criteria of multiple base use of a single square waTe. Each of these wave- forms require three times the number of square wave inverters for three phase use as compared to single phase use. Another consideration, while not pertinent to the ground rules which established a four wire three phase connection, is whether the phase voltages can be connected in delta. In order to be connected in delta, the instantaneous voltage sums of the phases must be equal to zero. Wave.forms which meet this requirement are shown in Figures 4-28, 4-30_ 4-36, 4-38, 4-39, and 4-40. When using stepped waveforrns to synthesize a sine wave, it is usually necessary to filter the output voltage to reduce the total harmonic distortion. If harmonic elimination filters (LC tanks) are used to reduce the harmonic distortion, the new total harmonic distortion can be approximated by using the following equation: et i 2 _h-, l + 1 T.H.D. - I00 (_ - (i ) (4-8) where T.H.D. = total harmonic distortion e t - root-mean-square value of waveform before filtering ef root-mean-square value of fundamental component of waveform h = order of the harmonic to be removed by filtering Example: (4- I i Assume Waveform in Figure 4-33 is used in an inverter. What is the new 49 total harmonic distortion if a filter is used to eliminate the 7th and IIth harmonics ? e t ef h = i. 5055 V •, 1.483 V = 7 and ii Therefore / T.H.D. = I00/( i'5055_2 - (i + 1 11.483 ' Tz + 11",V T.H. D, i.o152i 2 - (z.o287i or a reduction of 17,4 - 4,36 x i00 ,, 74.9% 17.4 This method will determine what harmonics must be removed to meet a particular T.H.D. Specification. A. Note on Stepped Wave Analysis In the course of analyzing the stepped waves presented in this report, a useful mathematical method was developed. This method permits the user to write the Fourier series expansion of periodic stepped waves having axis symmetry and half wave symmetry by simple inspection methods described here. The waveform must first be normalized by setting the amplitude of the first step to a unit quantity and the amplitude of all the other steps as a function of this unit quantity. See Example 4-2. The series expansion is then written as a sum of sine terms with cosine coefficients as follows: = 4V F(lcosOl+aCOSO2+bcosO3+. " +_< coseNisinv_+ e TT u_ 1/3 (Icos 301 + acos 3_92+bcos 3(93+... +c_,cos3eN)s in3wt+ 1 ..... + _ (Icos(2n- l)_91+acos(2n- 1)E)2+bcos(2n- l)e 3+ .....+ _< cos (2n-liON)sin(2n-liwtl (4-9) _1 5O From this expansion it is possible to determine by elementary manipulation which harmonics cancel, the amplitude of any harmonic, and what step amplitudes or angular division must be varied to eliminate a particular harmonic. Example: (4-2) Assume the normalized waveform e(t) in Figure 4-41. The following equation may be written for this waveform (Figure 4-41). = 4V EcosOl+acosO2_bcosO3}stnwte 7T +1/3(cos30 l+acos302-bcos 303isin3wt +1/5 (cos 501+acos5O 2-bcos5G3isin5wt +1/7(cos70 l+acos702-bcos703isin7wt 1 +''" (2n-l) (c°s(2n-liOl+ac°s(2n-liO2 -bcos (2n-1 )0 3 )s tn(2n- 1 jwtJ (4- 1 O) Notice that the steps may be negative. Steps that descend rather than ascend are negative. If it is desired, for example, to eliminate the third harmonic from the waveform the coefficients (a) and (-b) can be changed to cancel the coefficient of cos30, thereby eliminating the third harmonic. HI. MAGNETIC COMPONENT STUDIES An optimum magnetic design requires not only optimization of the individual magnetic components (transformers, inductors, etc. ) of any given system but also, of equalimportanc% an optimum choice of the overall system to be used to perform the specified function. (For example, it will be shown that for purposes of paralleling transistors, under some conditions the use of the split transformer technique is superior to the balancing reactor approach from a weight and loss view- point. Clearly, when these conditions are encountered, regardless of how well the balancing reactors are designed, their use will result in a poorer overall system than could be obtained by other means, i What is optimum will depend on the specific application since in general, weight and losses cannot be simultaneously minimized. 51 To obtain quantitative means for optimizing a system of magnetic components, it is first necessary to determine the characteristics of each component in the system as one or more of its parameters are varied. Accordingly, the transformer (as a typical and common magnetic componenti was analyzed to see how its weight and efficiency varied with the size and design. In particular, analyses were made of: The optimum design of a transformer of fixed size to operate at a given power rating. i The variation of the size, weight, and losses of such a trans- former as its rating is varied. i The relationship between the size and losses of a transformer operated at constant power, 4i Multi-phase transformers and circuits utilizing tltem. The resu/ts obtained from these analyses were then used to investigate the relative merits of several common inverter circuit techniques. The areas investigated were: The weight and loss penalties for using switching elements that must be paralleled. A comparison between different techniques for paralleling. (Balancing reactors versus the split transformer technique_i i The use of multlphase transformers to provide simultaneous weight and harmonic reduction. These analyses and the results obtained from them follow. The mathe- matically more involved sections are found in the Appendices 2-I through 2-III of Quarterly I%eport No. 2 of the "Optimization Study of High Power Static Inverters and Converters" - NASA - CR-54021. A. Optimum LoadinK of a Fixed Transformer The general rule regarding the optimum loading of a transformer is that maximum efficiency occurs when the copper loss and core loss are equal. This result, which is derived in Quarterly Report No. 2 - Appendix 2-I (NASA- CK- 54021 ) under the as sumptlon that the primary copper loss due to transformer magnetization current may be neglected, can be expressed mathematically as 52 P_ _c - 1 (4-11) P r where P is the total core loss (hysteresis, eddy current, inter- laminar _nd stray losses) and Pr is a total copper loss (and includes, where applicable proximity- and skin effects but not, as indicated above, the copper losses due to the component of the primary current which serves to magnetize the core). This derivation, however, was based on the conditions of a constant input voltage and variable load. In practice, however, both the input voltage and maximum des ign load are generally fixed, and all that the transformer designer can vary is the overall size and/or shape of the transformer and the relative losses in the coil and core. To start, it will be assumed that the size and shape of the tranformer are fixed, and only the relative core and coil losses can be varied. For a core of fixed size, given material, lamination loss, induction level, and operating at a constant frequency, the only way in which the core losses can be reduced is to reduce the induction level to which the core material is operated. With a fixed size and voltage input, this can only be accomplished by increasing the number of turns on the primary (and hence, in order to maintain the required turns ratio, the secondary turns must be correspondingly increased). .% decrease in core loss in a constant size transformer is thus obtained at the expense of increased copper losses, since not only is the number of turns increased (increasing the winding resistance) but also with the total area available for winding remaining constant, the available cross- sectional area for each turn decreases. Taking these effects into account, and making use of the approximate empirical relationship P - c 1 B a (4- 12)C where P is the core loss/unit volume, B -, maximum flux density the coreCreaches, and c 1 and a are constant (for any given core material and operating frequency), it was shown in Quarterly P.eport No. 2 - Appendix 2-I (NASA-CR-54021) that the optimum ratio between core loss and copper loss is given by the equation Pc . 2_ (4-13) Pp. a where Pc and PR are defined as for Equation 4-11. 53 The relative losses in equal size and weight transformers carrying the same VA with one designed according to Equation 4-11 and the other designed according to Equation 4-13 are computed in Quarterly Report No. 2 - Appendix 2-I _[_d the results plotted in Figure 4-42. From this it can be seen that except for the case where a " 2 (where the two designs are equivalent), the losses in a transformer designed with equal copper and core loss will be greater than those in a trans- former designed for a core loss 2/a times the copper loss. The actual differences in loss are not very great, however, as can be seen from Figure 4-42. When these loss variations are translated into efficiency variations, the difference is further suppressed. B. Scaling of Transformers Ouce an optimum transformer is designed at a given power level, and its weight and losses determined, it is often useful to be able to scale the size of the transformer up and down over the power level and thus obtain new designs without extensive calculations. A decision on the various possible methods of paralleling can only be answered with a knowledge of the total transformer weights and losses in the different schemes. Therefore, some useful equations for the scaling of trans- formers will be developed here. These equations are strictly true only when used to compare transformers of similar construction operating at the same core flux density and copper current density levels. Consider a transformer with linear dimension L. The window area available for the coils, AW, is given by Aw_L2. For operation at any fixed current density, the cross-sectlonal area of each turn, A, is directly proportional to A W and inversely proportional to N, the total number of turns. Also, the current, I, that can be carried in each wire is proportional to the cross-sectional area of that wire. Writing these relations in equation form there results: A_ L 2 AWr,_L 2, At'_Aw , I_A I Ir-_ __.U_wtv__ (4-14) N N N Therefore, the ampere turn (NI) capability of the coil is given by 2 L L 2 NI _N (_--i " (4-15} When operating at any fixed value of maximttm flux density, the volt/turn which the transformer can support is directly proportional to the core cross-section, which is proportional to L 2. Therefore V _ L 2 (4-16) N 54 The volt-ampere rating of the transformer is thus given by: VI = V___(NI) _ L 2 (L2) = L 4 (4-17) N In other words, the rating of a transformer is proportional to the fourth power of its linear dimension. Its weight, W, on the other hand, is directly proportional to the volume which is proportional to the cube of its linear dimension W r",., volume z'-'L3 or W/V L 3 (4-18) (Actually, the weight equals (volume of iron x density of iron) + (volume of copper x density of copper1, but under the assumptions of the problem, the ratio of the volume of iron to volume of copper remains constant, hence the weight is proportional to the overall volume, even though this volume contains substances of different dens itie s. ) One possible figure of merit for a transformer, ratio, is then given by power ,. VI L 4 weight _- /_ _ = L Thus, the figure of merit for a transformer is proportional to its linear dimension. its power/welght By combining 4-17 with 4-18, the relationship between weight and power rating may be determined as follows: VI F,_ L4/-,-.(WI/3) 4 = W 4/3 or W = K (VIi 3/4 (4_20i Or, the power handling capability of a transformer is proportional to the 4/3 power of its weight, where k is a constant of proportionality. For the conditions under which the previous equations were derived (namely, constant current density in the windings and constant flux density in the core) the loss per unit volume (or weight) remains constant in all transformer sizes; thus, the total losses are directly proportional to the weight. Or rewriting Equation 4-Z0 after sub- stituting losses for weight, there results Loss _(VI) 3/4 (4-Zl) 55 The relationship between the size, weight, and losses of scaled transformers have thus been derived. It should be mentioned that in order for these relations to hold, the scaled transformers should all be similar - that is, all their (linear) dimensions should be changed in the same ratio. This is not a difficult restriction to meet in practice since, for example, all transformers made from a square stack of scrapless E-Ilaminatlons (which are all constructed with the same ratios) and having the available window area com- pletely filled with wire would fall into this category. Of course, the conductor and core material must be the same for all the transfor- mers. This analysis holds for either toroidal or laminated cores, single or three phase transformers, as long as the similarity condition is met. In general, smaller transformers may be designed with higher current and flux densities than larger ones due to the fact that it is easier to get the heat out of a smaller unit. This would reduce the weight of the small transformers but increase the losses still furthe r. C. Relationships Between Siz% Weight and Losses Quarterly l_eport No. 2 - Appendix 2-II of the "Optimization Study Of High Power Static Inverters And Converters" - NASA- CI_-54021 contains an analysis of the losses in transformers delivering con- stant power as their size (and hence weight) is varied, thus indica- ting quantitatively the trade-otis involved in transformer designs. The results of this analysis indicate that to obtain a transformer which operates at a fixed power level and has a minimum weight- loss product, the smallest transformer designed according to Equation 2-I-20 of Quarterly Report No. 2, (NASA - CI_-54021) in which the required core flux density is low enough so that Equation 4-12 is valid, should be used. In other words, the core material should be operated as close to its maximum flux density as possible without violating Equation 4-12. D. Multi-Phase Transformers and Circuits Utilizing Them Up to now, the analysis of transformer optimization has not had to involve any considerations outside the transformer, since the cir- cuitry associated with the transformer would not be affected by the optimization. This ceases to be the case when three-phase trans- formers are used, as will be brought out in the following discussion. 56 Of the various possible power switching stages which may be used for three-phase static inverters, some require the use of three single phase transformers, some work only with three-phase trans- formers and some may be used with either type. More complex transformer construction than the three-phase is also possible and sometimes useful. 11 In order to be able to use a three-phase trans- former, the instantaneous sum of the voltages applied to the three windings must equal zero at all times. This condition is imposed by the flux requirements of three phase transformer core design. This requirement is met, of course, by three equal amplitude sine waves each displaced by 120 °. It is also met by three equal amplitude quasi-square waves with an "on" time of 120 °. Three square waves, even though separated in phase by 120 °, do not fulfill this require- ment; thus, inverter power stages which produce square waves cannot use conventional three-phase transformers. The weight savings possible with three-phase transformers will now be investigated. The core geometry of a single phase transformer made from con- ventional scrapless E-I laminations is shown in Figure 4-43. If three of these would be combined into a single transformer, keeping the same coil dimensions and core cross-section, the three-phase transformer would have the core geometry as shown in Figure 4-44. If it is assumed that the stack thickness of the original transformer is x (i. e. the stack is square), then the thickness of the three-phase transformer stack will also be x. Since the coils used on the two transformers are identical, the only weight savings will be in the core. The volume of three single-phase cores of the type illustrated in Figure 4-43 will be 18 x 3. The volume of one three-phase core is shown in Figure 4-44 and will be 14.5 x 3. Thus, a saving of approx- imately 20% in core weight is achieved by the use of a three-phase unit. If_ for a rough estimate, the core weight is taken equal to the copper weight_ the overall weight savings will be about 10%. The core configuration of Figure 4-44 is not the only possibility_ any more than the single phase core shown in Figure 4-43 is the only one available; variation of the dimension ratios are possible and under some conditions quite desirable. (For exampl% because of the poorer primary copper utilization in static inverter transformers operating with the center-tapped primary scheme it is advantageous 11 Design Manual Featuring Tape Wound Cores, Magnetics, Inc. TWX-300, pp. 45-55 57 to have a larger window area than provided by the conventional scrapless laminations}. It is also possible to take advantage of the flux relationships existing in a three-phase system and arrive at a third _Epeof core structure, shown in Figure 4-45. The manufac- turer tZof this type of core claims a 10% weight saving over a conventional three-phase core configuration for this design as well as elimination of magnetic, electrical and physical unbalances caused by the unsymmetrical design of the conventional three-phase core. The drawback of this system is the added complexity of winding coils for it, particularly if it is desired to make maximum utilization of the window area. It has already been mentioned that, because of their special magnetic construction, three-phase transformers 1) are lighter than equivalent single phase units, require that the instantaneous sum of the voltages applied to them be always zero. This first item, is of course, an advantage. Single square waves cannot be used with the three-phase transformers since their instan- taneous voltage summations do not equal zero. Thus, in order to satisfy the second item, a more complex waveform must be used such as a quasi-square wave. To generate a quasi-square wave usually requires more components and more complex circuitry than a square wave, especially if zero clamping (refer to Quarterly Report No. 1, pp. B0 ff of the "Optimization Study Of High Power Static Inverters And Converters"} is required, thus offsetting the weight reduction obtained for the three-phase transformer in item one. However, the voltage requirement of the three-phase transformer can be used to provide zero clamping without the use of additional components. Consider the circuit and waveforms shown in Figure 4-46. If switches S 1 - S6 are turned on as indicated, it will be observed that 1) There are always two and only two switches on at the same time. z} Whenever both switches of any phase are off, the sum of the voltages being produced by the other two phases is zero. 12 Gulow Transformer Company, Inc. 58 Thus, whenever any phase has both power switches off (and hence its output voltage would, under normal single phase conditions, be undefined) in this three-phase system, the output voltage of that phase must necessarily be zero. Thus, zero clamping is provided by the power switches of the other two phases, working in conJunc- tion with the three-phase transformer. Because this circuit produced 1Z0 ° quasi-square waves without the need for any addi- tional zero-clamping components, it appeared quite useful and was investigated further. One item of interest is how the circuit handles load current which is flowing in the secondary of any phase during the dwell (or zero out- put voltage) time of that phase. This secondary current cannot be balanced by primary current from the same phase, since the only way that primary current can flow is either through the power switch or reactive diode, neither of which can occur when the output voltage is zero. Examination of the circuit and the magnetic rela- tionships required by the transformer showed that any such secon- dary current in one phase gave rise to equal currents in the primaries of the other two phases; (for convenience, a i:1 primary to secondary turns ratio was assumed) one of these induced currents was of such a direction as to represent an energy flow from the d.c. source (and hence went through a reactive diode). Since the two currents were equal, no net energy was transferred through the inverter to the output of that phase, a condition which must necessar- ily exist since no energy can be transferred under a zero output vol- tage condition. Because this extra current in the power switching elements does not contribute to providing any output power, it results in a less effec- tive utilization of the switching devices than would be possible with a simple square wave inverter. This problem of decreased switch utilization is not limited to this particular circuit, however, as a similar effect will occur in any circuit where the final output vol- tage is a result of the summation of individual voltage waveforrns which are not all in phase. Thurs, any of the circuits which provide for harmonic reduction and/or voltage regulation by adding different phased square waves will be subject to the same problem. However, due to the new wayinwhich the proposed circuit (Figure 4-46) operates, it was deemed advisable to actually compare the switching element currents in this circuit to those in the more conventional circuits which use phase shifted square waves for harmonic reduction. 59 The two circuits compared are shown in Figures 4-48 and 4-49. The line to neutral output voltage of each of these circuits is the same, both in amplitude and waveform, and is shown in Figure 4-47. In this waveform, the first harmonic is the llth, making for relatively easy filte ring. Regardless of whether SCPJs or power transistors are used as the power switching element in these circuits, it is the peak value of the current through the switch which is of interest. This is because in the case of transistors, the transistors themselves must have a cur- rent rating greater than the peak current, and with SCI_'s, the commutating circuit must be capable of turning the SCR.'s off under peak load current conditions. Hence, an attempt was made to deter- mine the peak currents which would occur in the power switching elements in the two circuits. For the case of the conventional cir- cuit utilizing single phase transformers as shown in Figure 4-48, it is quite easy to put an upper bound on the peak current since, with a peak current of I amperes flowing in each of the three phases, it is obvious that, with the turns ratios as given, the peak current in any primary could not exceed I(.67 +.5 + .16) = 1.33 lamperes. (The number associated with each secondary of the transformers is the turns ratio of that secondary referred to the primary; the angle given with each switch is the phase angle of the output of that switch section compared to the first, which serves as the reference.) Due to restrictions on the phase angles of the impedances which may (according to specifications as outlined in the methodology plan), serve as loads on this unit, it is impossible for the peak current in all three phases to occur simultaneously. Thus, the 1.33 I value is in excess of the actual maximum peak current which the switching elements may encounter. For the three-phase transformer circuit (shown in Figure 4-49), because of the complex fashion in which currents are transferred from one phase to the other two during the zero voltage periods, it is very difficult to see how to choose the individual phase loads (within the permissible load range) in order to maximize the peak current in any one switching element. However, one attempt to do this yielded a peak primary current of Z. 7 I amperes, which is over twice that obtained using the phase shifted square waves. 6O Since both circuits provide the same output voltage, and require the same number of switches, it is obvious that only half the peak cur- rent capability is required of the switching elements in the conven- tional scheme as compared to those in the three-phase transformer circuit. Since the three-phase transformer circuit also requires a more complex driving circuit, it appears that the 10% transformer weight advantage would be more than offset by the additional weight of the extra switch current capacity needed for operation with the three-phase transformer. A more complex transformer suitable for operation with an input set consisting of six square _vaves, each shifted by 30 °, has been des- cribed in the literature. This transformer contains six windows whose outer legs contain both the primary and secondary windings required for each of the six phases. This transformer will be referred to as a "hexadic" transformer because it contains all six- phase primary and secondary windings. PreLiminary investigation of the magnetic paths in this "hexadic" transformer indicates that it would not create the type of circuit problems that the three-phase transformer does. Like the three- phase transformer, the "hexadic" transformer obtains its weight savings by using less iron in those portions of the magnetic circuit where flux cancellations occur. It is estimated that the "hexadic" transformer is 20% lighter than its six single-phase equivalents. This general area of multiple inverters in connection with multiple transformers to produce stepped waveforms approximating sinu- soids will be pursued in more detail in the following sections. E. 3200 CPS Inverter (10KW) Power Sta_e Transformer Analysis a) Transformer Analysis An analysis was made of several possible transformer designs of a complex nature similar to the "hexadic" transformer des- c ribed by Kerntk_ Roof & I-Ietnrich. 2 The results of this analy- sis are given below. The basic technique used to reduce the weight of these trans- formers is to utilize the fact that the fluxes in different portions of the circuit are sometimes in such a direction as to cancel one another part of the time. Thus, some sections of the magnetic op. cir. 61 path may be made smaller than would be the case if the fluxes could not be depended upon to cancel. This cancellation generally occurs in inverter circuits which synthesizes a multi-stepped waveform from the addition of several square w_ves. Some cancellation will also occur in those inverters which vary the phase shift between two sets of output voltage to obtain vol- tage regulation. Consider the simple transformer for phase shift regulation shown in Fig- ure 4-50. The total volume occupied by the core of this transformer is x(4x)(3x)+2(x2)(8x) = IZx3+16x 3 = 28x 3. If this transformer is utilized in an inverter circuit where, for example, the input square wave to each outside winding varies between 25 and 31 volts, then, if the phase difference between the two input square waves is always adjusted to provide the same average value in the output (center leg) then the center leg does not have to be any wider than 25/31 (2x)=l.6x. If the phase shift between the two input square waves, when the input voltage is 25 volts, is still greater than zero, the center leg may be reduced still fur- ther. This is due to the fact that in a quasi-square wave (which is the output voltage of the center leg) the ratio of the rms value of the fundamental com- ponent of the wave to its half-cycle average increases with increasing dwell angle as shown in the graph of Figure 4-52. Even assuming that the largest center leg (1.6x) will be required, the amount of core material saved by this reduction is (0.4x)(x)(5x)=Zx 3 which is 7_0 of the original weight of 28x 3. This weight reduction was obtained by utilizing the known flux cancellation between the two phase shifted square waves. It is also possible to utilize the flux cancellation between the several square waves which go into making the multi-stepped output from each inverter set. For example, in the three- phase tra_nsforrner shown in Figure 4-53, the fact that the instantaneous sum of the voltages applied to the three windings is always zero means that _1 + (_2+(_3--0 and hence there is no need for a separate magnetic return path. However, as mentioned before, the requirement that _I+_2+(_3=0 precludes the use of three square waves as the input to this device. Since square waves are the most naturally obtained output of switching type inverters, this presents a difficult application problem. A similar problem exists with the improved three-phase transformer as shown in Figure 4-54. A combination transformer which simultaneously allows the addition of the outputs from two separate inverter groups and also provides for flux can- cellation between inverters of the same three-phase set is shown in Fig- ure 4-55. It should be noted that this transformer will perform the same function as three of the flux adding transformers of Figure 4-50. However, three of these transformers have a core volume of 3(28x3)=84x 3. Even if the center leg is reduced to 1.6x, their total volume is still 3(28x3-2x3) = 78x 3. On the other hand, the core volume of the transformer of Figure 4-55 is less than this by the amount saved by Joining the interior flux paths and 62 allowing for flux cancellation. This savings is 2(I 2/3x2)(7.6x)=25.3x 3. Thus, a core weight savings of 32. 590 over the best design of a single phase flux-addlng transformer is possible. This savings in core weight is accom- panied by a corresponding decrease in core losses over the single phase t runs form er app roach. A transformer suitable for use with the six square wave approximation to a sine wave is shown in Figure 4-56. As in the case of the transformer of Figure 4-55, the window length and depth (3x and 2x respectively) have not been optimized but were chosen only to keep the individual sections of the transformer on an equal basis with a single phase transformer as shown in Figure 4-51. Since the transformer of Figure 4-56 replaces six of the sin- gle phase transformers of Figure 4-51 (which have a core volu_ne of 6(26x_= 156x3,) and allows a savings in core volume of 5(15/6xZ)(7.6x)ffi69.7x 3, its core weight (and losses) will thus be over 45% smal/er than those of the equivalent single-phase transformers. Thus, this represents a considerable savings over conventional techniques. In additio_ the magnetic paths in these two transformers (Figures 4-55 and 4-56) do not require any special instantaneous voltage conditions to be met as do the conventional three- phase transformers. Clearly, the concepts embodied in the transformer designs of Figures 4-55 and 4-56 may be extended to handle any number of input square waves. However_ all the transformers discussed so far have been extensions of the conventional design in only two dimensions. Accordlngly_ investigations were started to determine if any significant advantages could be had by usin_ core configurations that were basically three dimensional. Although most of these would be impractlcal to construct out of conventional laminated core materlals_ the use of ferrites, powdered iron 7 or similar materials capable of being moulded could render such designs feasible. Two configurations which were investigated and found to possess no apparent advantages over more conventional designs are shown in Figures 4-57 and 4-58. A configuration for the three dimensional replacement for Figure 4-56 is shown in Figure 4-59. This configuration is obtained by bending the two ends of Figure 4-56 around until they meet. Savings are obtained by this maneuver because the path formed from the two ends can be made smaller than the algebraic sum of their cross-sections because of the flux canceUatlon that will occur. The amount saved in this configuration over the fiat one of Figure 4-56 is is 8. 3 5 % of the weight of the equivalent single-phase transformer system. Howeverp not only the constructional difficulties but 63 also the heat transfer and mechanical stability problems en- countered with this type of construction are considerably increased. Thus, based on the relatively small improvement obtained by using this system over the "two-dimensional" trans- former of Figure 4-56, this technique does not appear practi- caUy useful. A comparison between this technique and the use of_two "hexa-Z dic" transformers, as described by Westinghous% will now be attempted. The total core volume of the core of Figure 4-56 amounts to 86.3x S. If a "hexadic" transformer core is designed so that it provides the same core cross-sectional area and window area/winding as the six phase-flux adding unit of Figure 4-56, it will have a core as shown in Figure 4-60 and a total core volume of 4Z 1/9x 3. Since two of these are required to provide the same output as a single unit of the type of Figure 4-56, their total core weight will be 84 Z/9x 3, still less than the six-phase flux adding technique. However, when the winding weights are fac- tored in, the total weight of the two "hexadic" transformers becomes 4267x 3, whereas the total weight of the six-phase flux adding transformer is only Z635x 3, making the six-phase flux adding transformer more desirable from the standpoint of re- duced weight and less copper loss. Both of these designs yield a transformer with much more weight in copper than iron; an improvement in both could be expected with a detailed design effort, but it is expected that the flux adding transformer would still come out ahead, basically because its design permits splitting up the secondary from the primary, yielding more but smaller coils having a lower mean length per turn for the same volt-ampere capability. Hence, the flux-adding construction depicted in Figure 4-56 has been chosen as the type of output transformer that will be used. b) Core Material Considerations Besides the core configuration used, other very important parameters are the core material to be used and the flux density at which it will be operated. In general, those types of core 64 materials having low losses (Molybdenum Permalloy) also have low saturation flux densities, and materials having high satura- tion flux densities (Supermendur) also have high losses. The 50% nickel-iron alloys (such as 48 alloy) have saturation flux densities and core losses which are between the two extremes mentioned. Which one will make the best transformer core depends on what is an acceptable weight-loss distribution. (This, of course, will vary from system to system and hence no one answer will be satisfactory for all cases. ) As an aid in visualizing the trade-offs involved, a sample trans- former was designed and (theoretically) operated at various fre- quencies and power levels. This was done for three different types of core material: Square Permalloy 80 (which is repre- sentative of the low-loss, low saturation flux density materials); Supermendur (which represents the high loss, high saturation flux density materials); and Orthonol (which is representative of the medium loss, medium saturation flux density materials). The transformers were all simple two-winding toroidal units with equal copper and core weights (1 lb. core and 1 lb. copper, for a 2 lb. total weight), and the excitation was varied in such a way that the core loss and copper loss were always maintained equal (unless it was impossible to obtain the desired core loss because of core saturation). In this case (core saturation), the applied voltage and hence, core loss was limited to a maximum value as determined by the saturation flux level and further increase in output power was obtained by increasing the output current only, holding the input voltage (and hence flux level) constant. The results of this investigation are shown in Table 4-5 which shows the core flux density, core loss, output vol- tage, current and power and total loss for the three different core materials operated at five selected frequencies and many different power levels. The indicated frequencies were chosen because manufacturers' data on core losses were available at these frequencies. The power levels at which each transformer was operated at any given frequency were selected to give the desired values of copper loss (between 0.3 and 50 watts) and to result in equal core and copper losses whenever possible (i. e., core loss not limited by saturation). The results shown in Table 4-5 are also plotted on the graphs of Figures 4-61, 4-62 and 4-63. The points at which the core losses can no longer be increased to keep up with the copper loss (because of core satur- ation) are indicated on these graphs by a circle (O). 65 For example, these graphs indicate that at 400 cycles for this particular transformer weight (two pounds), if only low power is required ( _ 8Z watts) then the core material which will yield the lowest loss is the square Permalloy 80. In the medium power range (SZ to 480 watts), Orthonol is best, while for high powers (480 to 1100 watts) at this weight level, Supermendur is best. As a specific example, at the 300 watt level, a two pound trans- former of this design would have a loss of 8.5 watts with an Orthonol core, Z8 watts with a square Peramlloy 80 cot% and 13.5 watts with a Supermendur core. Thus, at this power and weight level (and at 400 cycles)_ the Orthonol design would be best. However, if any of the three parameters (frequency, weight, power level) changes, the optimum core material might also change. As the last example shows_ the curves in Figures 4-61, 4-6? and 4-63 can be readily used directly to determine the optimum core material for a two pound transfor- mer (of the specific toroidal design arbitrarily assumed for pur- poses of this example) at any of the five selected frequencies. To obtain the optimum designs at other weights, the graphs of Figures 4-61 through 4-63 can still be used, but appropriate modifications must be made according to the scaling equations developed in a previous section. (See Section III-B - Scaling Of Transformers). As an example of the application of these equations, consider the problem of making an optimum choice for the core material of a 300 watt transformer weighing 10 lbs. (again operating at 400 cycles). By Equation 4-Z3 of this report_ this is equivalent_?3core_ flux density and winding current den- sit_ to a 300(--_) -" -- 35. 1 VA transformer that weighs two pounds. Chedl_ing the 400 cycle curves for the lowest loss 35.1 VA transformer, the square Permalloy 80 design is super- ior, with a total loss of 0.7 watts. Since the loss is directly proportional to the weight, the losses in the 10 lb. 300 VA are (1-_0)(0.7) = total 3.5 watts. Thus, it cantransformer be seen that the proper (lowest loss) choice of transformer core material depends on the weight and power rating of the trans- former in question; the Z lb. 300-watt transformer used Orthon- ol core material, while the 10 lb. 300-watt transformer used square Permalloy 80 core material and had 5 watts less loss than the Z lb. Orthonol design. 66 By repeating this scaling process as described above for several different weights at constant power, a curve of minimum loss versus weight can be obtained. Such a curve is shown in Figure 4-64 for Z800 VA at 3000 cycles and shows that the lighter the transformer, the greater the change in losses for a given change in weight. On this curve, the point at which the optimum core material changes turns out to be at 28.8 pounds, and is so indicated on Figure 4-64. Which of the designs represented by this curve should be selected will depend on the weight penalties, addi- tional losses placed on the DC power supply, and heat sink a s s embly. c) Use of Shunts for Current Limit A very simple technique for providing current limiting is the incorporation of magnetic shunts between the input and output windings of the output power transformer. These are merely pieces of iron of the same laminated material as the core and located so that the flux setup in the core by the primary winding may pass through the shunt without linking the secondary. An example of this is shown in Figure 4-65. In order to avoid having all the flux pass through the shunt, thus preventing any power from being delivered to the secondary_ an air gap is inserted in the shunt path. This air gap determines the way the flux divides between the shunt and the secondary winding under any given loading condition. A detailed analysis of the operation of the magnetic shunt (given in Quarterly Report No. 3 - Appen- dix 3-]I of the "Optimization Study Of High Power Static Inver- ters and Converters" - NASA - CR-541ZZ), indicates that as long as the shunt (or rest of the transformer core) does not saturate, the transformer with an internal magnetic shunt can be represented by an equivalent circuit consisting of an ordinary transformer with a linear inductor in series with its secondary. This is indicated in Figure 4-66. ]_ the magnetic shunt of Figure 4-65 is selected so that under short circuit conditions_ the transformer output current is Z00% of the rated (full load) load impedance, then the value of the series inductor in Figure 4-66 will be one-half of the'rated load impedance. If the magni- tude and phase of the load voltage provided by this transformer are plotted as a function of the (resistive) load, the results are as shown in Figure 4-67. As can be seen from this graph, when the load is up to full rated, the output is about 10g0 lower than it 67 would be without the shunt, and the phase shift is 26.6 ° . Thus, for three-phase applications with unbalanced loads, the use of magnetic shunts for current limiting introduces serious voltage regulation and phase shift problems. However, since by speci- fication the battery supply usually varies over a 30% range, in a single phase system where the phase shift w_ld not be impor- tant, the additional 10% change in output voltage over the load range could be compensated for by operating the voltage regula- ting system over a slightly larger range. Detailed design pro- cedures for current limiting transformers may be found in the literature. 13 d) Use of Holes in the Iron Core for Current Balancing Although it is not expected to be needed in this inverter because of the input voltage decided upon (56 volts) and the increasing availability of silicon power transistors with very high current ratings, a technique for incorporating the balancing reactors into the output transformer core, as suggested by the NASA technical manager, was investigated and will be described below. Figure 4-68 indicates the configuration that was investigated - a section of the transformer core in which three (assuming three transistors are to be paralleled) holes are placed. The common current Bus A is split into three Wires B, C, and D each of which is passed through one of the holes in the core. A second Wire E is looped through all three holes in such a way that as one travels along this wire, the core material is always traversed in the same direction. Currents flowing in Wires B, C and D set up magnetic fields as indicated in the core; these link with the loops of Wire E causing a current to flow in it. This current is in a direction opposite to the current in Wires B, C and D, tending to cancel the magnetic fields that the cur- rents in those wires originally set up. Since the same current must flow in all parts of the Wire E, only ifthe three currents in Wires B, C and D are equal will all the magnetic fields be cancelled. Otherwise, they will not, and the uncancelled fields will cause voltages to be induced between the common and 13 "Design Procedures For Special Type High Temperature Transformers - I/'. Irving Remis, Electrical Manufacturing, August, 1957, pp. l19ff. 68 separate ends of Wires B, C and D, in such a polarity as to tend to equalize the currents in the three wires. Thus, this system acts in the same fashion as the closed chain balancing reactor scheme discussed in "Paralleling Techniques and Problems" - Section IV- B-b of this report. (In order to avoid interactions between the flux setup by this balancing scheme and that produced by the main power windings on the transformers, these holes should be located out of the main flux path, possibly in little nibs incorporated in the transformer lamina- tion punching. For those materials having a high retentivity (Orthonol and Supermendur), it may also be necessary to intro- duce an air gap into the magnetic circuit by slitting the core from an edge to each hole. ) IV. PARALLELING TECHNIQUES AND PROBLEMS Regardless of the exact nature of the inverter transformers, the switch- ing elements can be considered as an entity. When the output required of any power switching stage is greater than can be handled with one switching device on each side, the power handling capability of the switch must be increased by paralleling. The simplest method of paralleling is to connect additional power switching elements in parallel with the original one. Although simple, this method suffers from the drawback that, because of the unavoidable differences in inter- nal impedance of the switching elements, the load current will not be shared equally. Two non-dissipative paralleling techniques, the split transformer technique and the balancing reactor technique, can be used to force current sharing between the parallel power switching elements. These will now be analyzed in turn to determine their relative merit. A. The Split Transformer Technique The essentials of the split transformer technique are shown in Figure 4-69. Here, the original (unparalleled) circuit requires a power switching device with a capability of VI watts. The lower circuit indicates the technique used to split the load up into N equal parts_ with each power switching stage being required to handle only VI/N watts. Because all the transformer secondaries are connected in series, the same current flows in each, and thus, through transfor- mer action, the primary currents are forced to be identical. This method achieves exact load sharing at the expense of splitting up one large transformer into N smaller ones. The weight and loss penal- ties that this entails are obtained from the following analysis. 69 It will be assumed that all of the smaller transformers are identical to one another and similar (in the geometrical sense) to the single large transformer; that is, with all dimensions scaled inthe same ratio, the smaller transformers can be made congruent with the large one. The smaller transformers will also be operated at the same core flux density and winding current density as the larger ones. The analysis proceeds as follows: Let the large transformer have a power rating of PI" Then each of the smaller transformers has a rating of PI/N. If the weight of the large transformer is W D then, by Equation 4-20, WN, the weight of each of the smaller ones can be obtained as follows: W I = k PI 3/4 W N = k__l_) 3/4 = Wl (4-22) N N 3/4 Thus, the weight of N of the smaller transformers will be W 1/4 N (NI/_) : WIN (4-23) which is N I/4 times as much as the weight of the single large trans- former. Since, under the operating conditions assumed above, the losses are directly proportional to the weight, the losses in the N smal- ler transfo_ners w_t,I be N 1/4 times the losses in the larger t_ransformer. B. Balancing Reactor Techniques The weight (and loss) penalties incurred in using the split transfor- mer paralleling technique have already been analyzed (Equation 4-23). Those due to another current balancing scheme, the use of balancing reactors, will now be investigated. A comparison of using a balancing reactor to equalize the currents in two switching units versus the use of a split output transformer to achieve balance will be examined first. The two methods are shown schematically in Figures 4-70 and 4-71. The balancing reactor technique operates on the principle that, unless the currents in the two halves of the reactor are equal, a voltage is developed across the inductor in such a direction as to increase the current in that switch tending to carry the least current. Because the same switch will always tend to slack, the balancing reactor must always provide the same polarity voltage when load currents are flowing in it. Thus, an air gap is required in the core to allow the flux to return to zero dur- ing the non-conducting halves of each cycle when no current flows and 70 the core must reset itself for the following half-cycle. This air gap, coupled with the relatively few turns required to support the small unbalance voltage results in the balancing reactor having a fairly high magnetizing current. (This could be reduced by over-design of the voltage capability of the unit). The magnetizing current flows through the switch which normally tends to carry more than its share of the load. Therefore, unlike the case of the split transformer tech- nique, in the balancing reactor technique the currents in the switch- ing elements are never perfectly balanced, the unbalance being due to the magnetizing current of the balancing reactor. In the simple scheme shown in Figure 4-70, the output transformer is rated at 2 Io V volt-amperes (where V is the supply voltage and Z I ° is the DC current taken by the switching stage), and the balanc- vo ing reactor is used at Io _ volt amperes, where v is the maxi- mum voltage difference required across the switchin_ elements to obtain the desired current balance. However, because of the uni- directional nature of the reactor current, only one-half of the B-H loop of the core of the balancing reactor can be utilized; thus, since only one-half of the voltage capability of the reactor can be utilized, its size and weight will be comparable to one of twice its normal VA rating. Therefore, for purposes of weight and loss estimates, the VA rating of the balancing reactor will be taken as 2 (I o v__o) . ioVo" From Equation 4-20, the weight of the single output transformer plus two balancing reactors for the balancing reactor technique will be W 1 = k [2(IoVo)3/4 + (2 IoV) 3/4] (4-24) Similarly, the weight of the two split transformers will be W z = 2 k (IoV) 3/4 (4-25) The ratio of these weights is: wl k [zt%vo)314+tz%v)3/4]_i + (V__q_°)3/4 (4-26) " Zk (ioV)3/4 v This ratio is plotted in Figure 4-73 for different values of will be less than I (i. e., the balancing reactor technique will be lighter) for (__9_)3/4 _ 1 - 1 _[ v o ]V 4 A/Z or V 4/31-4 /z V o, and 'V (4-27) 71 For a typical V o of 1.5 volts for a silicon transistor, the cross-over supply voltage for the two techniques (from Equation 4-27 or Figure 4-73) is 18 volts. Above this value, the balancing reactor circuit of Figure 4-70 is lighter (and has smaller losses); below it the split output transformer technique is best. For balancing more than two switching elements at a time, there are several methods that may be used. The split transformer technique as shown in Figure 4-69 may be used. Balancing reactors of the type shown in Figure 4-70 may be connected in cascade; an example of this for the case of balancing four units is shown in Figure 4-72. Although this technique (Figure 4-7Z) requires a minimum number of reactors for the number of transistors to be paralleled, it has the disadvantage that if any one of the paralleled elements develops a fau/t and is cleared from the circuit, the current in the remaining elements is no longer balanced, accelerating failure in the remaining switches. a) Reference Balancing Technique One method of avoiding this problem is shown in Figure 4-74. Here the balancing reactors serve to maintain a constant ratio between the current in the reference switch and the current in each of the paralleled power switches. Should one of the power switches be cleared from the circuit, all the switches, including the reference, will pick up proportional shares of the load. (If the reference switch fails, the balancing scheme becomes inop- erative; for this reason, the reference switch is generally operated at a reduced power level to enhance its reliability.) As an example of this operation, consider the circuit of Figure 4-74 and assume 1) All the switches are operating 2) The total load current is I 3) The turns ratio of the comparison reactor is 5:1 so that the reference switch current is 1/5 of the power switch current. Let the power switch current be x. Then, the total current is 5(x) + x/5 = I (4-z8) 72 which has the solution x - . 192L Thus, each power switch carries . 192I arnps and the reference switch carries . 0385 I. If one of the power switches opens, the equation for current division becomes 4 (Xl) + Xl = I (4-29) This has the solution x 1 = . 238 I; each power switch now carries • 238 I amperes and the reference switch carries .0476 I. The currents are still balanced, although they are, of course, higher than when all switches were operating. As in the case of the simple circuit using only one balancing reactor, the actual switch currents will deviate from the ideal due to the magnetiz- ing currents of the balancing reactors. An analytical investigation of the weight penalties inherent in the reference balancing technique will now be undertaken. If there are n power switches and the current through the reference ele- ment can be neglected, the current in each reactor will be I/n, where I is the total current carried by the parallel switch bank. Since two switching banks are used for each inverter stage, the total number of reactors needed is 2n. Each reactor must be able to support v o volts (where vo, as before, is the maximum un- balance voltage between switch units when all are carrying equal current). Thus, the rating of each reactor (again inserting a factor of two to account for the reduced use of the core capability brought about by the unidirectional current), will be Z VoI/n amperes. The ratio of the weight of this system to one consist- ing of n split transformers if then wt. of reference balancing technique __ wt. of split transformer technique (VI)3/4+ 2n(ZVQI-_-)3/4 n _ 3/4 n -1/4 2v o )3/4= n + Z (__ (4-30) V where Equation 4-Z0 was used to evaluate the relative weights. Thus, it can be seen that the weight (and loss) advantages of this system increase as the number of elements to be paralleled increases and as the supply voltage increases. As a specific example, with v o = 1.5, V = 28 and n = 6, using Equation 4-30 yields a ratio of 73 wt. of reference balancing technique = 6 -1/4 + 2(_-g) 3/4 wt. of split transformer technique - z.o13 (4-31) Thus, under these conditions the split transformer technique is only marginally better than the reference balancing reactor technique and other considerations would probably be the decid- ing factors. b) Closed Chain Balancing Reactors Still another technique using balancing reactors is shown in Fig- ure 4-75. Here, each switch has its current balanced with the two elements on each side of it (and the outside ends are com- pared with each other, to form a closed chain). With the loop closed, the balancing obtained by this technique is very good; when one of the switches is opened, the loop is opened and the unbalance increases, although the circuit still operates to main- tain the balance. If the current carried by the reference tran- sistor in the previous method is neglected, this shceme has the same weight as the reference balancing scheme. It does have the advantage that all of the switches are treated equally; any- one can fail and the circuit will still operate somewhat. (In the case of the reference balancing scheme (Figure 4-74) failure of the reference switch means complete loss of balance, although balance will be maintained even though one or more of the power switches fail). As the example worked out in Equation 4-31 shows, neither technique (split transformer or balancing reactor) offers any great weight advantage over the other in the power level and vol- tage range under consideration. However, weight (and losses) are not the only items of significance. But when multi-aperature transformers are used, splitting them is better than using balancing reactors. In conclusion then, the selection of a certain balancing reactor technique versus the split output transformer technique in regard to weight savings can be found for any given switching element voltage unbalance v o by using the cross-over graph of Figure 4-73. 74 V. GENERAL DESCR/PTION OF PROPOSED 3200 CPS - 10KW INVEI_TEI_ DESIGN The overall block diagram of the complete inverter is shown in Figure 4-76. The master crystal oscillator-pulse shaper provides a series of output pulses at 12 times the inverter output frequency. These are fed to two places: 1) a six-phase transistorized flip-flop reference ring counter which provides an output consisting of six squares waves, (at the inverter output frequency) each displaced from the next by 30 °, and 2) a phase shifter, which is capable of delaying the pulses from the crystal oscilla- tor by any amount from (approximately) 15 ° to 175 ° as measured at the fundamental frequency. The pulse output of the phase shifter pulse sha- ping network , which has the same appearance as the pulse output directly out of the master crystal oscillator-pulse shaper, is then fed to another six-phase transistorized flip-flop phase shifter ring counter iden- tical to that mentioned above. Its output is another set of six square waves at the inverter fundamental output frequency with each displaced from the next by 30°_ and the entire square-wave output set displaced from the corresponding ones provided by the reference ring counter by an amount depending on the delay provided in the phase shifter circuitry( (15 ° - 175°). These outputs (six from each ring counter) are then ampli- fied by their associated pre-drive buffer amplifiers and fed into the input of the square wave power switching stages where they are further ampli- fied and transformed by various ratios on the output transformer to be added in series with one another to yield the composite output. With this technique, the output voltage shown in Figure 4-47 contains no harmonics lower than the llth. This scheme of utilizing all six square wave output voltages to form part of each phase output voltage was chosen in preference to a similar scheme which generates a comparable waveform with the use of only five of the six available waveformsUbecause the method of using all six square wave voltages gave a more complete distribution of phase loads and allowed all twelve output transformers to be identical. The "hexadic" transformer described in the above-mentioned report could still be used in this scheme. Although the generation of an even more complex waveform than that provided by the six square wave approxima- tion would permit a further decrease in filter sir% this was not attempted because a more complex system than the six-step approach could not then be scaled down without becoming overly complex for its function at the lower power levels. (The next possible number of steps in a scheme of the type used here is nin% which would mean a 50% increase in the over- all complexity.) It should also be mentioned that the filter in a static 11 op. cit. 75 inverter performs two functions; it not only removes unwanted harmonics from the power stage output, but also acts as a buffer between the power switching stage and the load. The delay of the phase shifter circuitry is controlled by the voltage feed- back circuit to maintain the average of the phase voltage outputs at the desired value (or peak current in any or all phases below the Z00% over- load limit). The individual blocks are discussed in more detail in the following secttons. VL POWER STAGE A. Final Transformer Design Using the information obtained in the Magnetic Component Studies (Section III) of this report, it is now possible to establish final trans- former designs for the 10KW- 3200 CPS - Static Inverter. Since the lowest weight-loss products were obtained by operating the transfor- mer core materials at as high induction level as practically possible, the output transformer was designed in this fashion. Three different core materials were used and for simplicity and ease of comparison, the core losses and wtndin_ losses were designed to be equal. Alu- minum foil is used for the windings, both for weight savings and ease of fabrication, since at 3200 cycles, only a few turns of relatively large cross-section are needed. The lamination design for use with a low-loss, low saturation flux density material such as square Permalloy 80 is shown in Figure 4-77. The center leg of this core is only 1.3 times the width of the outer legs because of the fact that the phase shift between the two input square waves will never be less than Z2 °. Thus, while each outer leg must support 61.6 volts of square wave, the inner section only has to have enough volt-second capability to support a quasi- square wave with Z2 ° dwell angle and amplitude of (this is the worst condition) twice the minimum battery voltage (44.8 volts). This ]_as^_ a volt-second equivalent of a s uare wave of amplitude 2 (44.8)(l_.u-_ zz) = 78.6 volts which is only - iq28 times that of the maximum 61.618U volt square wave which will appear across each primary winding when the battery voltage is at its maximum. Although of all rectangular shapes the square provides the least perimeter for a given area and hence is desirable as a core cross-section because it allows the least winding resistance for a given volt-second capability, it is obviously impossible to make both the inner and outer legs have a square cross-section since they are of different widths. As a compromise, the stack thickness was chosen to be the cube root of 76 the product of the two primary and one secondary widths or 3 _/ (1.0)(1.0)(1.3) = 1.1. The window length was arbitrarily chosen and the window width was calculated so as to give approxi- mately equal weights of core and winding. The designs for the three different core materials are summarized in the table below. TABLE 4-6 De s igns I II HI Core Material Sq. Perrn- 80 (z rail) Orthonol (2 rail) Supermendur (Z rail) Core Size As shown in Figure 4-77 As shown in Figure 4-77 X 0.69 As shown in Figure 4-77 X 0.48 Core Loss 4Z watts 88 watts 191 watts Primary Winding (Each of IZ) Wind two coils 16 turns each bifiltar. Alumi- num foil cross- section . 018" x 1.78" Wind two coils Z0 turns each bifiiiar. Alumi- num foil cross- section . 010" x 1.23" Wind two coils 25 turns each bifiliar. Alu- minum foil cross-section .0057" x 0.85" Secondary Windings COIL 1 8 turns COIL Z 5 turns COIL 3 4 turns Aluminum loll cros s- section .035"xi. 78" COIL i 9 turns COIL Z 7 turns COIL 3 3 turns Aluminum foil c ros s-section O. ZI"xl. 23" COIL I iZ turns COIL Z 9 turns COIL 3 3 turns Aluminum foil cross-sectlon .011"x0.85" Maximum Operating Flux Dens ity 7 KG IZKG 20KG Coil Losses (Total) 42 watts 88 watts 191 watts Core Weight i0.5 Ibs. 3.5 Ibs. l.Z Ibs. 77 TABLE 4-6 (continued) Designs I II Ill Winding Weight i0. i ibs. 3.4 Ibs. I. 15 Ibs. Insulation I. 4 lbs. 0.5 lbs. 0. Z Ibs. TOTAL WEIGHT ZZ. 0 tbs. 7.4 Ibs. Z. 55 lbs. Total Losses 84 watts 176 watts 382 watts Wt. - Loss Product 1860 Ib-watts 1300 lb-watts 975 Ib-watts Efficiency (at I0 KW load) 99.16% 98.37% 96.32% It can be observed that going from Design I to Design II allows a weight reduction of 14.6 pounds while increasing the losses only 92 watts, for a trade-off at 6.3 watts/lb. On the other hand, in going from Design H to II_ 206 watts must be sacrificed for a reduction of 4.85 lbs., giving a trade-off ratio of 42.5 watts/lb. As indicated earlier, which design would be selected depends on the weight-loss characteristics of the rest of the power system. In order to arrive at a firm design and weight-loss figure, the transformer design using Orthonol (Design H of Table 4-6) will be selected. This represents a middle-of-the-road design, which does not lean too heavily toward either extreme of efficiency or minimum weight. B. Transistor Configuration A typical power output stage is represented in Figure 4-78. The power switch transistors are represented by Q9 and Q10 while trans- former T1 is part of the power output transformer. Calculations indicate that in the flux adding IZ step approximation, under the worst possible conditions, (200% load on all three phases and worst combination of load power factors), the peak current which will have to be carried by any one side of a power switching stage will not exceed 88 amps. 78 With bifiliar primary windings on the output transformer T1, the peak voltage appearing across any of the power switches should occur at turn-off and will be twice the supply voltage plus the di/dt voltage introduced by the delay core T4. The latter will depend on the satur- ated inductance of the delay core and is not expected to exceed 10 volts. The supply voltage does not exceed 61.6 volts (56 V + 10%) making a maximum switch voltage of 2(61.6) + i0 = 133 volts. Both these voltage and current requirements can be met by a single transistor appearing recently on the market - the Silicon Transistor Corporation #STC-2501 which has ratings of 150 amps and 150 volts. Although the current rating provides plenty of margin_ the voltage rating is rather close. It is expected, however, that it will not be long before the units can be made with voltage ratings to 200 volts, which would provide a considerable margin in the voltage also. Westinghouse can already make 30 ampere units with voltage ratings to 300 volts. Should higher voltage units not be available and larger safety factors (or higher input voltages) be desired, there are two possible methods which may be used. 1) Several of the existing 30 amp high voltage (300 V) transistors may be paralleled in order to provide the required current carrying capability. At least 3 would be required to be paral- leled to handle the 88 ampere peaks; this would require the use of split transformers or some type of balancing reactors thus introducing additional weight, loss and complexity. Provisions would also have to be made in the base drive circuitry to insure proper sharing of the drive power. z) Two (or more) of the 150 V, 150 A transistors could be con- nected in series. This permits the high voltage to be divided between them. Since power switching transistors of this type generally fail in the shorted mode, should one fail {short) it would not have to be removed from the circuit. However, the drive losses and forward losses in this circuit are twice those in the single transistor circuit. Furthermore, any net- work used to equalize the voltages across the two transistors cannot have very low impedance, because it should not cause a circuit mal- function when one of the transistors shorts and the entire voltage appears across the other one. 79 Because of the additional problems and losses that these multiple tran- sistor techniques involve, it has been decided to use only one 150A, 150V transistor in each switch. The 150V collector to emitter voltage of this transistor is the largest voltage rating that can be obtained for this size transistor at the present time. Thus, the maximum voltage safety factor is only 10% which is well below the safety design margin of 100%. How- ever, collector to emitter voltage ratings of Z00V and higher are expected to be available in the near future therefore increasing this safety factor to 50% and higher. To protect the transistors from voltage spikes of any source, zener diodes are connected across them. The proposed power stage is shown in Figure 4-78. The delay transformer T 4 serves the purpose of preventing the load cur- rent from flowing through the power switches (Q9 or QI0) until some i0 _4 secs. after they have been turned on. This reduces the turn-on losses in the transistors to a negligible value. This transformer will support 60 volts for 10 _ seconds. It weighs about . 06 lbs. and at 100% load has copper losses of Z. 4 watts and a core loss of 1. Z watts, for a total of 3.6 watts. This core saves the turn-on losses in Q9 and Q10 which, at full load, are estimated to total 9.6 watts. Thus, the savings are six watts per output stage or 7Z watts total for the inverter through the use of the delay cores. This is at the full load case; at lighter loads the savings will be less; at heavier loads, more. For example, at the 200% load point, the savings amounts to 100 watts. Current feedback is used to provide the necessary base drive current for the power transistors Q9 and QI0" This type of base drive has the advan- tage over a more conventional voltage base drive scheme in that a con- siderable reduction of base drive losses can be obtained. This reduction is obtained for two reasons: 1) The amount of base current supplied is instantaneously and con- tinuously adjusted so that only the required drive is provided; thus excess, unusable drive is avoided. z) The feedback circuit makes the drive circuit appear as a current source (in the forward direction) to the input (base). Thus, power wasting base current limiting resistors necessary when driving the transistor from a voltage source, are not required. At full load, the drive requirements for a single transistor is approxi- mately Z. 5 watts. (This is actual power delivered to the output translstor.) With a proportional drive, this is approximately the amount of power that the drive would supply. On the other hand, if the drive is furnished by a circuit that always supplies the maximum drive that the transistor would 80 ever require (whether it is needed or not) the power delivered to the transistor would be about 8 watts. In addition, the current limiting resis- tance required in order to avoid problems due to the change in input vol- tage of the output transistor with load and output current would dissipate another 8 watts. Thus, the proportional drive allows savings of about 27 watts/power stage -_3Z0 watts total. In addition, the drive used for this inverter also provides for the turning off of one side of the power stage before the other side iB turned on, thus reducing the switching losses. A base drive proportional to the collector current is obtained by adding to the base drive transformers (T2, T3) , a winding through which the collec- tor current passes. TZ and T3 then act like current transformers in which the primary winding is the collector feedback winding and the secon- dary (load) winding is the base drive winding. With the proper polarity and turns ratios on the two windings, the result is a large amount of posi- tive feedback which results in the power transistors (Q9 or Q10 ) being turned completely on and the current being limited solely by the external load. When it is desired to turn off a transistor which is being held on with this feedback technique, it is necessary to provide enough turn-off current from the external driving source to completely cancel the posi- tive drive signal provided by the collector feedback winding. This is provided by the drive circuitry discussed in the Logic section - Section VII- D of this report. In order to avoid excessive reverse base voltages on transistors Q9 and Q10, two diodes are placed in each of these transistor base drive cir- cuits in the reverse direction in order to limit the base to emitter reverse voltages of these transistors to -1.4 V DC maximum. This reverse vol- tage of-1.4V DC will insure that these transistors will remain cut off over the highest operating ambient temperatures. These diodes also pro- vide an approximate voltage match with the base drive voltages (+1.4V DC) when the transistors Q9 and Q10 are in their respective '1on" states. Short circuit protection for the output stage is described in the Logic Section - Section VII - E of this report. It is generally desirable to provide additional windings for the reactive diodes on the output transformer primary (TI) as shown in Figure 4-78. If the tap voltage is properly choser b this provides a slight forward bias on the reactive diodes when their associated power transistors are con- ducting. This bias_ just under that required to cause significant conduc- tiorb allows that reactive diode to begin conducting without the output voltage of the stage having to change from the (E-forward switch drop) to 81 the (E + reactive diode drop) as must occur when the reactive diodes and power switches are connected to the same point. This reduction in output voltage shift with a primary current shift from the power switch (transistor) to the reactive diode results in a lower power stage internal impedance under reactive loading and thus reduces the effect of unbalanced loads on the voltage regulation and phase separa- tion of a three-phase inverter which does not have individual phase voltage or angle regulation (as is the case with the present inverter). However, because the amount of forward bias required for the reac- tive diodes is so slight, because of the high values of volts/turn obtained on the power transformers of high power inverters opera- ting at higher frequencies, voltage increments of the size required (Iv 0.5 volts) are too small to be obtained without the use of frac- tional turns on the output transformer. Although this is possible (by passing the last turn through a hole in the core, thus linking only a fraction of the core flux with that turn), it is not practical, and hence will not be used. C. AC Filter Because of the widely varying load impedance encountered, conven- tional filter design techniques are generally not applicable to the design of fitters for use with static inverters. For some special cases where the load magnitude and impedance variations are restricted, special filters can be designed which compensate for the internal regulation of the inverter. 14 However, in the more common situation where the filter phase shift and voltage transfer ratio must be held nearly constant in spite of wide variations in load impedance and power factor, the filter configuration shown in Figure 4-79 is most applicable. Because the series section is tuned to resonance at the fundamental frequency, there is no attenuation or phase shift of the fundamental in passing through this filter. The amount of atten- uation of any given harmonic is dependent on the relative impedance of the series and shunt sections at the frequency of the harmonic. In general, it is desirable to have as small a filter as possible, both from the point of view of weight and efficiency and also transient load regulation. 14 "OTT" Filter - Westinghouse Silicon Controlled i_ecttfier Designer's Handbook" - First Edition, 1963 pp. 7-18 to 7-22 and pp. 8-1 to 8-8. 82 For the twelve-step waveforrn which will be used in this inverter, the first harmonics present besides the fundamental will be the eleventh and the thirteenth. As the two twelve-step waveforms are varied in phase with respect to one another, the harmonic content of the sum will vary. Since the phase displacement will be varied by the voltage regulator in such a fashion as to maintain the fundamental component of the sum constant as the battery voltage is increased, the phase displacement will increase. The harmonics in each wave- form will increase in proportion with the battery voltage. The har- monics in the ouZpuZ will vary in a more complex fashion because for certain phase displacements, some of the harmonics in the two wave- forms will cancel one another. The percentage of total harmonic distortion and the percentages of the 1 lth and 13th harmonics in the sum of two twelve-step waveforms as a function of the phase displace- ment between the two waveforms is shown in Figure 4-80. Figure 4-81 shows the value of M required of the filter for the llth and 13th harmonics as a function of the phase displacement between the two input waveforrns. The value of IV[ is defined as the ratio of the mag- nitude of the series reactance of the fundamental over the magnitude of load impedance at full load. These values for M were obtained from the consideration that no single harmonic in the output should have a value in excess of 2% of the fundamental In the case of the llth and 13th harmontcs_ it is this requirement, rather than the 5% maximum on total harmonic distortion which is the most stringent. Because of the impossibility of obtaining the exact number of turns required on each winding for proper cancellation of the harmonics, there will be some harmonics in the output which would ordinarily be cancelled. However, the actual number of turns on each winding can- not differ from the correct value by more than 1/2 turn, or a total of Z (I/Z) turns out of a possible 19 on the three windings (for Design II in Table 4-6). This is for two of the windings being off by 1/Z turn; thus, the amount of harmonics re-introduced in this fashion should not exceed 1/19 or 5. Z5% of the value of that harmonic in a square wave. These amounts are shown below. TABLE 4-7 Harmonic Percent in Square Wave Residue in Output 3rd 33% 1.75% 5th zo% 1.o5% 7th 14% O. 75% 9th 11% O. 58% 83 If all three windings were off by 1/2 turn, the half-turn on one wind- ing would cancel the effect of the half-turn on another winding, leaving a net error of only 1/2 turn. Since none of the llth and 13th harmonics are cancelled by the inter- connections, having the turns ratios inexact neither increases or decreases the magnitude of these harmonics, which are limited by the filter to a maximum of 2% each. The total harmonic distortion contributed by all the harmonics through the 14th is then given by | THD(%) -/(1.75) 2 + (1.05) 2 +(0.75) 2 + (0.58) 2 + 22 + 22 3.6% This is considerably less than the 5% total prescribed by the specifi- cation, especially when one considers that at no time (except zero phase shift, which is not a region of normal operation) will all of the harmonics reach their maximum values simultaneously. Since the load may vary in power factor from i. 0 to 0.7 lag_ each phase (line-to-neutral) may draw as many as 3300 sin (cos-10.7) = 2300 vats. Since the shunt capacitor of the filter draws only 830 vars, it is actually advantageous to eliminate the shunt inductance and use the load to provide the missing inductive vats for tuning. In fashion, the full load power factor as seen by the inverter, ranges from .97 lead to .84 lag instead of the 1.0 to 0.7 lag of the load. Also, by using the load inductance as part of the filter, the weight and losses associated with the shunt inductance are completely eliminated. _ E2_ ¢ii0_ 2 Since the full load impedance is i_L - _-- -3.uz3u_03 = 3.66 and a value of M (from Figure 4-81) of 0.23 provides adequate attenuation, the required series inductance is h = l_h(0.23) - (3.66)(0.23) - _J (6.25)(3. 2XI03) .0419 x 10 -3 hy - 41.9_hy. Part of this inductance is made up of transformer leakage inductance which is estimated to be approxi- mately 28.2 _hy. The maximum current this inductance will be required to carry occurs at the 200% toad condition and is I = (3300) (2) (_/_-- I01 amps (peak). The design current will max Ii0 .84 " be 30A rms (100% load). The core design is shown in Figure 4-82. The series capacitor required for tuning this choke is: 84 1 . 1 - 59.z C - 6J X c (_.'66)(0.23)(6.28)(3.2x103) A 55_fd ±2% capacitor will be specified; the small additional capacity required to exactly tune the capacitor with the core will be added in parallel. The maximum rms voltage across the capacitor (under the 200% load condition) will not exceed 55 volts; at steady state condi- tions under i00_ load the capacitor will be 27 volts. (rms). The shunt capacitor is related to the series capacitor by the Equation Cp - M2C S and thus has avalue of(59.2)(.23) 2 . 3.12_fd. It is operated at IZ0 volts rms AC. (Under steady-state conditions, the voltage across the shunt capacitor is independent of the load. ) D. DC Filter The DC input filter for the +56V supply will consist of a shunt capaci- tor whose value is tentatively set for 100_fd at 200WVDC. A small m ic a-capacitor with a rating of. Ol_fd at 500 WVDC may be placed around this large capacitor for high frequency noise suppression. The input (DC) filter actually serves several functions: It helps attenuate the effects on the supply line of the pulses of current drawn by the inverter. In so doing, it not only suppresses a consider- able amount of radio frequency noise that would otherwise be imposed on the DC supply lines but also makes the supply appear "stiffer" to the inverter, thus avoiding wild and possibly damaging voltage fluc- tuations at the inverter input terminals. It also is capable of suppressing any voltage pulses on the supply line which tend to affect the inverter. It thus decreases both the conducted radio frequency interference produced by the inverter and the inver- ter's susceptibility to conducted i_ F. I. on the input lines. Because of the relatively slow switching speeds (10_sec) of the large silicon power transistors used in this type of inverter, the amount of radio frequency interference generated above 200KC is expected to be quite small. Therefore, no difficulty is expected in meeting an i_. F.I. specification such as MIL-I-26600 which requires suppression down only to 200KC. To suppress any voltage transients of this nature which may get through, as well as any generated internally in the inverter, zener diodes will be connected across all appropriate t ransisto rs. 85 E. Weights and Losses One of the largest contributors to the total inverter weight is the out- put transformer. As indicated in a previous section, the output transformer design can be varied to exchange weight for losses; which design would be selected depends on overall system considera- tions such as the permissible weight, size and cooling capacity of the required heat sinks and the weight and capacity of the external power source which is unknown at this time. For this report the compromise design using Orthonol (Design II) was used. The trade-offs in the design of the AC output filter inductors follow the same lines as those for the output transformer; variation in the core materials can provide different designs for different applica- tions. Hence, only one AC filter choke will actually be designed; it is to be understood that extensions to other core materials would parallel the output transformer designs. The filter choke was designed to have an inductance of 13.7 microhenries, carry a current of 30A rms (corresponding to full (100)% load current) and to not saturate with peak coil currents as high as 101 amperes (which corresponds to the case of 200% load at . 7 power factor). Since the leakage reactance of the output transformer, calculated to be Z8.2_hy (the total effective leakage reactance, referred to and summed up in the series connected secondary windings which make up each of the three phases), can be considered to be effectively in series with the output of the power output transformer (as is the series filter tuning reactor), the series filter reactor was reduced from 41.9_hy by the amount of the leakage reactance (28.2_hy) to only 13.7_hy. The core configuration is shown in Figure 4-82, and the other electri- cal and physical parameters of the choke are given below: TABLE 4-8 Core: Coil: Coil loss: Core los s: Core Weight: Coil Weight: Total Weight: Total Loss: 2 rail Orthonol, as shown in Figure 4-8Z Aluminum foil; cross-section 0. 025" x 0.900", 13 turns 1.5 watts (full load, 1.2 watts O. 155 lbs. O. 075 lbs. O. Z50 lbs. Z. 7 watts 0.92 P.F. load) 86 The remaining items in the power stage which dissipate appreciable power are the delay core, power switching transistors, reactive diodes, and base limlting diodes. Magnetic components such as the delay cores were not designed in detail hence, their weights and overall losses were only estimated. Their dissipation under full load conditions are shown below: Power Transistors : Forward current loss: Z(18.6)2(0.01) = 7 watts/palr Turn-on-losses (none, because of delay core) Turn-off-losses (Tfall= 1O_sec) = 13.6 watts/pair Off-losses - 6 watts/pair Drive-losses (Proportional drive) = 2.5 watts/pair Total output transistor loss = 30 watts/pair or 360 watts for the entire inve rter. The losses in the reactive diodes will depend on the battery input vol- tage as well as the load, because the phase shift between the two input square waves in each phase will be varied by the voltage regulator to compensate for input DC voltage changes. At the nominal input vol- tage (56 volts) the phase shift between corresponding square waves will be about 80 °. Thus, the current in each phase will be out of phase with the voltage by 40 e. Hence, the current rhough the reactive diodes will have an average value of i. 9 amperes each. With an average diode drop of i. 0 volt_ the total loss in the reactive diodes in each stage will be 3.8 watts, or 46 watts for the entire inverter. Total weights and losses for all the 3200 cps - 10KW power stages are estimated as: TABLE 4-9 Delay Cores T 4 . Z lbs. 10.8 watts Driver Transformers T 2 and T 3 1.5 lbs. 10 watts Diodes Dll - D14 0.4 lbs. 25 watts Diodes D17 - DI8 i. 0 lbs. 46 watts Zener Diodes DZ 5 - DZ 6 1.0 Ibs. Neg. 87 VII. LOGIC A. TABLE 4-9 (continued) Output Transistors Q9 - QI0 AC Filter Capacitors DC Input Filter Capacitors AC Filter Inductors Output Transformer - T 1 Total Weights and Losses S. 3 ibs. 360 watts 9.0 Ibs. 3.0 Ibs. .75 ibs. 8. i watts 7.4 lbs. 176 watts 29.55 ibs. 635.9 watts Os cillator The reference oscillator package unit (see Figure 4-83) will contain a crystal oscillator and a squaring circuit. The crystal oscillator will have an output frequency of 38.4 KC or IZ times the output fre- quency. The frequency accuracy will be maintained at ±. 02% over a temperature range of -550C to +85°C without an oven. This frequency stability of ±. 02% is inherent in the quartz crystal design that is used for this crystal oscillator. The squaring circuit shapes the waveform of the crystal oscillator into a square wave whose output will be 5 volts peak into a 5K load. The rise time of this square wave will be no greater than 130 nanoseconds. An external pulse shaping network (see Figure 4-83) is provided for this oscillator in order to supply the pulse energy necessary to step the reference ring counter and input flip-flop of the phase shifter. The oscillator output square wave is current amplified in the emitter follower circuit Q3- The resultant square wave output of this emitter follower is differentiated by the network consisting of C 1 and 1%3. The leading edge of this differentiated signal turns on the inverter QZ which places the base of the output emitter follower at ground momen- tarily. This allows a pulse current to flow from the flip-flop trigger circuitry to ground through resistor i%1 and logic diodes D Z and D 3 causing a change of state in the reference ring counter and input flip- flop of the phase shifter. This sequence is repeated for each incom- ing square wave. The emitter follower Q1 is required to supply the necessary ground pattx for the trigger circuits. The logic diodes D Z and D 3 are used as an "or" circuit to isolate the input flip-flop trig- ger circuitry of the phase shifter from the trigger circuitry of the reference ring counter. 88 B. l_in_ Counter Two ring counters are required for this inverter. One ring counter is used as a fixed reference to supply the necessary square waves to the reference driver stages. The second ring counter is used as part of the phase shifter circuit for output voltage regulation. Its square wave outputs are phase-shifted with respect to the reference ring counter by delaying its incoming steering pulses. Each ring counter consists of six fllp-flops whose output steering resistors are con- nected such that each incoming pulse will cause the ring to advance one step. Figure 4-84 is a typical flip-flop circuit used in the ring counter. Terminals 13 and 14 and resistors R 9 and RI0 are used to steer the next flip-flop in the ring. Similar input steering signals are supplied to this flip-flop from terminals 15 and 16. Figure 4-86 helps to illustrate these steering connections. Because the flip-flop is a bistable device, emitters of transistors O 1 and QZ are biased slightly above ground for the single ended supply. This will allow the bases of transistors O1 and 02 to be biased slightly negative with respect to their emitters to allow stability over a wide temperature range by minimizing the effects of the leakage current (Ico ). A 3.9 V zener regulated supply consisting of RII and DZ 1 is used for each ring counter to bias the emitters of the flip-flops. A start preference circuit consisting of resistors 1_1, 1_Z and capa- citor C 1 is used for each ring counter to set the "on" and "off" states of each flip-flop in the ring counter when the DC from the regulator supply is turned on. This insures that both ring counters are "set" with respect to each other so that proper tracking will take place when the pulses from the oscillator are introduced into their steering circuits. The outputs (3) and (4) are taken from the collectors of transistors Q1 and Q2 of each flip-flop circuit. In order to minimize loading effects on the ring counter, their outputs are amplified by the Darlington cir- cults used in the pre-buffer stages. C. Phase Shifter In order to obtain phase control between the two ring counters for vol- tage regulation, a phase shifting circuit is required. There are a num- ber of approaches that may be used to obtain this phase control; such as: 89 I) Phase shifting the output square waves of the phase shift ring counter with respect to the reference ring counter. z) Phase shifting the incoming pulse train to the phase shift ring counter with the use of a voltage controlled-varlable frequency oscillator. 3) Phase shifting the incoming pulse train to the phase shift ring counter with a cascaded phase shifting circuit. The first approach requires the use of a phase shifting circuit such as a push-pull magamp connected to each set of output leads of the phase ring counter. A slave flip-flop will be required on the output of each push-pull magamp to provide square waves of the same frequency (3200 cps) as the ring counter. The square waves generated by the ring counter are delayed by the amount of control signal applied to the magamp control windings. This approach offers the advantage of low operating frequency (3200 cps). However, it has a major disadvantage in that the gains of all the phase shifting circuits must be closely matched in order to prevent the out- put square waves from becoming shifted with respect to each other causing an increase in the harmonic distortion. The transient re- sponse time must also be very closely matched in order to provide uniform correction. The second approach utilizes a voltage controlled variable frequency oscillator to produce the second pulse train. Voltage feedback is used to control the frequency of this oscillator and hence the phase relation- ship between the reference pulse train and the pulse train generated by the oscillator. When the feedback error is corrected, the voltage controlled oscillator is held in frequency synchronism with the mas- ter oscillator. This means of phase control has the disadvantages that the voltage controlled oscillator must have a minimum drift with temperature and must be insensitive to transient overshoots during error correction that will cause positive feedback by allowing the square wave of the phase shift ring counter to slip into the 180 ° to 360 ° region. The third approach consists of six controllable delay circuits that are connected in cascade. This is necessary to produce the desired phase shift of up to 180 ° between the two ring counters at the fundamental frequency of 3200 cps because the reference pulse train must be de- layed by six (6) times its period. 9O This circuit has the following advantages: i) Response time can be made less than one period of the funda- mental frequency. 2) A phase shift greater than 180 ° cannot be obtained thus pre- venting the phase shift ring counter from slipping into the 180 ° to 360 ° phase shift region. 3) A variance in phase shift in any of the individual cascade stages will accumulate as a resultant output phase shift error which will be corrected by the voltage feedback circuit. This circuit has a disadvantage in that it must operate at a high fre- quency of 19.2 KC or six (6) times the fundamental frequency. The third approach was decided upon as the means of obtaining the required phase shift control because of the advantages it offers over the other two approaches. Because of the high operating frequency ( 19. Z KC) involved, an all solid - state circuit was considered to have certain advantages over an equivalent magnetic Circuit. At these high frequencies, the exciting current increases sharply for magamps, causing a reduction in gain and increasing its rise and fall time. Figure 4-87 represents a typical stage used in this phase shifting scheme. This typical stage consists of an input flip-flop, two linear ramp generators, a Schmitt trigger, and an output flip-flop. Linear voltage ramps with a Z. 6 _s period are generated by the cir- cuits that contain the PNP transistors O 1 and OZ. A constant charg- ing current is established by the voltage regulator circuit consisting of DZ I and I%1 which places a fixed voltage of 5.6VDC across resis- tors R Z and R 3 through the transistors Q1 and OZ which are connected as emitter followers. This voltage regulator circuit supplies the rest of the ramp generators from Point 18. The constant current is used to charge up the timing capacitors C1 and CZ, producing Linear vol- tage ramps at their outputs. These linear ramp generators are synchronized by the input flip-flop which alternately discharges the timing capacitors C 1 and C Z through transistors O3 and Q4 on each half cycle. Zener diodes DZ Z and DZ 3 are used to remove the base drive to the clamping transistors on al- ternate half cycles since the output of the saturated side of the flip-flop is 3.9 volts above ground. 91 The two linear ramps are introduced into the base circuit of the Schrnitt trigger through an "OR" circuit consisting of diodes D 1 and D 2. The input error signal from the differential amplifier is also introduced into this base circuit through resistor 1),6and Point (i0). This input error signal current biases the linear ramps which in effect shifts them up or down with respect to the present trigger level of the Schmitt trigger. This causes the Schmitt trigger to fire at different points on the ramp as a function of the magnitude and polarity of the input error signal. When the ramp voltage is below the trip voltage of the Schmitt trigger, transistor Q6 is saturated and transistor 05 is off. When the ramp voltage exceeds the trip voltage, the Schmitt trigger changes state by regeneration through resistor i_Ii. Transistor 05 saturates turning off transistor Q6- A positive voltage on the collector of O6 is placed at the inputs of two "AND" circuits composed of transistors O 7 and O8. Either transistor Q7 or Q8 will saturate when both signals on its input circuit are positive. I( one of the signals is at ground, then the tran- sistor will remain cut off. Thus, when the positive signal from the Schmitt trigger is combined with the positive synchronizing signal from the input (lip-(lop, the transistor in one of the "AND"circuits will saturate causing the output (lip-(lop to change states. The output flip-(lop serves as the input flip-(lop to the next stage and will steer the output (lip-(lop of that stage as it was steered in the previous stage. Since the error signal is applied equally to all the Schmitt triggers in this phase shifting scheme, an accumulative phase shift composed of the individual phase shifts will be obtained. The output of the last flip-(lop in this phase shifting scheme is differ- entiated into pulses which alternately saturate transistor QZ twice a cycle of 6F, (See Figure 4-89). Thus, a train of phase-shifted pulses are obtained at IZF or the same frequency as the input pulses to the phase shifter. These phase-shifted pulses are introduced into the steering circuits of the phase shift ring counter by the emitter follow- er circuit consisting of transistor QI. Transistors and diodes wlth very short switching times were used throughout the phase shifting circuit. Metal film precision resistors with low temperature coefficients will be used in the ramp generator and Schmitt trigger circuits for accuracy. Silver mica-capacitors with at least 5% accuracy will be used in the ramp generators. 92 De Additional trimming capacitors and resistors may be required in these ramp generators to obtain the same slope characteristics. The Schrnitt triggers may also require a trimming potentiometer to set their threshold levels in order to minimize errors. Driver The basic driver and its pre-drive circuitry are shown in Figure 4-90. The function of the power stage and its components are explained in the Power Stage - Section VI-B of this report. Examining this power stage reveals that it requires two basic modes of control. i) Pulse drive to turn off the power transistor that is saturated. z) Sustaining drive that is used to supply enough base drive to sustain the power transistor that is conducting and to back bias the power transistor that is off. The above modes of control must be supplied from the outputs of the ring counters. There will be one Power Stage for each ring counter f_ip-flop outpRt_ thus requiring twelve (iZ) Power Stages. In order to match the low level logic of the ring counters to these power stages, a pre-driver stage is required. A typical pre-driver stage is shown in Figure 4-90. The outputs of the ring counters are buffered by the Darlington circuits composed of transistors O1, OZ, O 3 and 04. This circuit is used to minimize loading of the ring coun- ters. The output of transistors 03 and 04 are connected in a push- pull inverter configuration to output transformer T 7. The secondary of this output transformer is used to supply the two basic modes of control. Examining the control circuitry for one side of the power stage, Fig- ure 4-90 (09 and TZ) note that the following events happen: 1) At the beginning of the positive half-cycle, transistor 0 9 is turned on (saturated) and transistor Q10 is turned off (unsat- urated). 2) Transistor Q5 is driven into saturation for a period of 10/_ s by the timing core T 5 at the beginning of this positive half- cycle. 93 3) 4) 5) 6) I 7) 8) 9) 1o) 11) During this 10_s time interval a large current, limited by resistor 1_19 (_,_i. Z A min), passes through a secondary winding N 4 of transformer TZ. The polarity of the current and the turns ratio are such as to set up a flux which will oppose the feedback current required to supply the base drive to power transistor Qg" Transistor Q9 is turned off with the cancellation of its base "drive. The sustaining drive transistor Q7 is held off during this time of 10_s since its base is placed at ground through transistor QS- The timing core T 5 saturates after 10_s removing the base drive to the shorting transistor QS- Its current is limited by resistor 1_9. The sustaining drive transistor Q7 saturates causing a current to flow in the secondary windings N3 of T 2 and T 3. The polarity of the current and the turns ratio are such as to back bias the base of the power transistor Q9 by._-- -1.4V to insure that the leakage current will not forward bias the power transistor at the maximum operating ambient temperatures. The sustaining drive forward biases the base of power tran- sistor Q10 by approximately +1.4V, turning it on. The power stage remains in this state until the beginning of the next half-cycle when steps 1 through 11 are repeated for the opposite side of the power stage (power transistor Q10 ). The timing cores T 5 and T 6 are reset on the negative half-cycle respectively. During the first 10_ s of the reset half-cycle, a reverse voltage is developed across the base drive circuit of the shorting transistors Q5 and Q6. Diodes D 9 and D10 are used to insure that the emitter to base voltage limits are not exceeded during this reset interval. Zoner diodes DZ 3 and DZ 4 are used to suppress voltage transients that may exceed the collector to emitter voltage ratings of shorting transistors Q5 and Q6- Logic diodes D 5tl_rough D 8 are used to isolate the two sustaining drive windings on transformers "I'2 and T3. The 94 t( current in the sustaining drive is limited by resistors R13 and 1%14 since the base drive of the power transistors Q9 and Q10 represents a non-linear load. Logic diodes D1 and D2 are required to keep the +56 V out of the base circuits for the sustaining drive transistors Q7 and Q8. The voltage drop caused by diodes D1 and DZ and the satura- tion voltages of Q5 and Q6 will not be enough to turn on these tran- s istors. E. Short Circuit Current Limitin_ The short circuit current limiting feature is used to protect the inver- ter against overload currents exceeding 215%. This is accomplished by turning off the power stages for a finite time and then turning them back on. The cycling will continue as long as the short remains. This sustained cycling will not be detrimental to the 3Z00 cps Static Inverter because of its low duty cycle (Du_10-5). However, a time delay cir- cuit could be added which would stop the cycling after a predetermined time if the short circuit persisted. A manual reset will be required on this time delay circuit to re-start the inverter. The current over- load circuit is shown in Figure 4-92. When the voltage regulator is first turned on, B+ (1) is supplied to the oscillator, ring counters, phase shifting circuitry, and a time delay circuit. This allows enough time for the oscillator and ring counters to stabilize before B+ (Z) is applied to the pre-driver stages. The time delay circuit consists of timing elements I%14 and C3 (see Figure 4-9Z). Capacitor C3 charges up to the threshold voltage of UJT-Q7 (16 V) in approximately two seconds. The UJT-Q7 fires caus- ing transistor 06 to saturate. The saturation of 06 pulses transfor- mer T9 whose secondary turns SCR1 (Gate turn-off type) on. The SCI%I switches on the controlled B+ (2) voltage which is used for startup of the pre-drive buffer stage and for current overload protection. B+ (Z) voltage is then applied to the pre-driver transformer T7 (see Figure 4-90)_ This initiates the drive necessary to turn on the power stages. This B+ (Z) also energizes transistor Q8 which clamps the timing capacitor (C3) to ground thus de-energizing UJT-Q7 and tran- sistor Q6. Pulse transformer T9 is current reset by resistor 1%18. Current transformers T1, TZ and T3 are used to sense the load cur- rent in each phase. The core material (HY MU-80) for these current transformers is operated at a very low flux density to prevent core saturation on current overload. Their secondaries are loaded by burden resistors 1%9, 1%10 and R11 to maintain the ampere turns relationship between their primary and secondary windings. The 95 three phase output voltage developed in the secondary windings of these current transformers is brldge-rectified and filtered by resis- tor R7 and capacitor CI to 0.6% ripple. Potentlometer 1%8 is used to adjust the output voltage by controlling the secondary load impedance of the current transformers. The fil- tered DC output is current-ampllfled by the emitter follower Q4. The threshold voltage is adjusted by potentlometer 1%8 to cause the Shockley diode to switch on at 215% overload. When the Shockley diode DAI fires, a large positive voltage is introduced into the base circuits of transistors Q3 and Q5 causing them to saturate. When transistor Q3 saturates, it causes transformer T7 to apply a pulse of 20_s to the base of the Darlington circuit composed of power transistors Q1 and Q2. The saturation of Q1 turns off all twelve power stages through the "O1%" circuit composed of twenty-four diodes of which one power stage is represented in Figure 4-90 by diodes DI9 and D20. This causes a large current to flow in the secondary wind- ings of T2 and T3 which will oppose the feedback current in whichever side happens to be on thus removing the base drive to the power tran- sistors Q9 and Q10. At the same time the saturation of transistor Q5 pulses transformer T8 which in turn reverse-biases the gate of the SCK1 thus turning it off. This removes the B+ (2) to the pre-driver stages of Figure 4-90, deactivating the sustaining drive and pulse drive to all twelve power stages. The transistor clamp (Q8) on the timing capacitor CB is also removed allowing the timing circuit to be initiated again. As soon as the power stages are turned "off" the overload current drops to zero. This removes the voltage from the emitter follower circuit Q4 which in turn allows the Shockley diode DAI to reset. Transistors Q3 and Q5 are turned off, removing the current from the pulse transformers T7 and T8. The pulse transformers are current reset through resistors 1%2 and 1%19. After a two-second time delay, the SC1%1 is pulsed on again. If the short circuit is still present, the overload cycle will be repeated until the short is removed. The response time of this circuit should be 312_s or less. The re- sponse time of the current transformers, 1%-C filter, and pulse trans- formers will be the major factors contributing to the overall response time of this overload circuit. 96 In this current overload scheme, the phase shift ring counter was not shifted back to 180". However, the phase shifting circuitry in Figure 4-87 can be shifted back to 180 ° to allow for soft starting after an overload to allow for a gradual increase in the output voltage. This soft starting feature was not included in this design since the response of the overcurrent circuit and the time delay before turn-on will be more than adequate to protect the power stage circuitry. F. Voltage Feedback The line to neutral voltage of each phase is measured by the potential transformers (Figure 4-92) T4, T5, T6 whose core material (Orthonol) is operated at a sufficiently low flux density to prevent core saturation due to large voltage excursions. The secondaries of these potential transformers are connected in a push-pull rectifier configuration and their center taps connected together and grounded to form a return path. Thus, each diode (D8 - DI3) will conduct 60" of its full cycle being biased off the rest of the time. This circuit is a slight depar- ture from the straight three-phase bridge configuration which requires that the secondaries of these transformers be connected in either a Wye or Delta configuration. Each diode only carries one-half the current and offers less effect on the output voltage if it should fail open as compared with its three-phase bridge counterpart. An addi- tional advantage is obtained with this circuit in that the diode voltage drop is less than half of that obtained for the bridge circuit. The out- put of the rectifier is filtered in the two stage filter composed of resistors P_IZ, l_Z4, and capacitors CZ and C4. The ripple should be attenuated to _. 06% by this filter. Resistor 1_13 serves as a stabili- zing resistor which determines the load current through the diodes and hence controls to some extent the diode drops. The output (9) of this filter is placed into one side of a differential amplifier which has a minimum input impedance of ?OK, which is determined by the gain hFE of the transistors 03 and Q4 and the collector and emitter resis- tors R1 through 1_4. (See Figure 4-94). A compensated reference zener diode DZ 1 is used on the base input of Q4 to establish a reference for comparison of the error signal. The gain of the differential amplifier is determined by the ratios of resistor i_I to R2 and resistor I_3 to R4, and is tentatively set for 50. The output of the differential amplifier (10) is placed into the base circuits of the six Schmitt trigger circuits (Figure 4-87) in order to bias the linear ramps and obtain a resultant phase shift. 97 The differential amplifier is compensated for drift caused by varia- tions in ambient temperature with the use of PNP transistors Q1 and Q2. The overall drift should be less than I ZA_,V/'C. A further reduction in drift can be realized by matching the NPN transistors Q3 and Q4 for gain and base to emitter drops. Metal film resistors wlth low temperature coefficients and +1% tolerance will be used in this amplifier circuitry. In addition, a separate regulated supply may be required to minimize the effects of B+ variation. An additional stage of filtering may be required on the output of the rectifiers to reduce the ripple by another order of magnitude in order to allow the gain of the differential amplifier to be increased. If higher gains are required to obtain closer tolerances on the output voltage regulation, a second differential amplifier may be used whose inputs are taken from the differential outputs of the first differential amplifier. The response time of the voltage feedback circuit will be determined by the complexity of the R-C filter network used, the potential transformers, the output power filter, and output power transformer. G. 200 Watt Voltage P_egulator An input voltage regulator is required for the low level logic and pre- buffer drive circuitry specified in Sections A through F. The maximum load requirement for this logic circuitry is approximately 5.5 amps at an operating voltage of +25V ±1%. The unregulated input supply vol- tage can vary from +61.6V to +44.8V low with a nominal value of +56V. A conventional series or shunt regulator may be used. Because of the large load requirements (,_/137 watts) the losses incurred by these regulators become prohibitive. (The conventional series regu- lator will have a maximum dissipation of 200 watts. ) A switching type regulator was used to minimize these regulator los- ses. This regulator was designed for 200 watts capacity to provide a satisfactory margin of safety. The maximum projected power loss for this switching type regulator is approximately 20 watts which is a factor of ten (10) less than the conventional series regulator. Figure 4-96 represents the basic voltage regulator circuitry. The voltage regulator circuitry is discussed in detail in Quarterly l_eport No. 3 - Page 132 to 137 of the "Optimization Study Of High Power Static Inverters and Converters" - NASA- C1%-54122. 98 VIII. RELIABILITY STUDY AND SCALING FOR 3200 CPS (10KW) STATIC INVERTER A. Results of Reliability Study A reliability analysis was performed on the electrical circuitry and their electrical components for the proposed 3200 cps Static Inverter. Packaging techniques and electrical connections were not included in this reliability study. The results of the study can only be used as a design guide to point out the circuits and compo- nents that have marginal designs, since the electrical circuitry was created from a theoretical design with no actual stress measure- ments being taken on the circuit components. The detailed reliability analysis is given in Appendix 4-II. The reliability block diagram that is used to represent the overall circuit configuration is given in Figure 4-II-1. Each block repre- sents a major circuit while sub-blocks are used to designate the individual circuits or components that are required to create a major circuit. The generic failure rates, derating factors, and environ,mental operating modes are established for each electrical component along with its operating time. From this information the total failure rate _ T is established for each block {see Figure 4-II-l) and its sub-blocks which may be used to determine which circuits need to be improved. The overall Reliability Figure of Merit R for the 3200 CPS - 10KW Static Inverter is then found from this information for each mission profile and is: l) Twenty-minute missile launch and one month continuous operation as a satellite in an earth orbit. a) _ i ti = .037175 b) R = .963506 2) Twenty-minute missile launch and one year continuous opera- tion as a satellite in an earth orbit. a) --_ i ti - .3Z9858 b) R = .718930 The overall Reliability Figures of Merit R (R = .963506 and R = .718930) are rather low and can be improved. Examining Figure 4-II-i reveals that the power stages (Blocks I and 5), the 99 B. pro-drive buffer stages (Blocks G and H), and the phase_shifter circuitry (Block C) have the largest total failure rates (AT). These large failure rates were caused by the large number of circuit com- ponents required, their percent operating duty cycles, and the de-rating factors assigned to each circuit component. These fail- ure rates can be reduced by selecting components with larger de- rating factors, a redesign of the circuitry to reduce its total number of components, or using redundant circuitry. Of these three approaches, the use of redundant circuitry on all circuits with large failure rates will greatly improve the overall Figure of Merit 1_ for this inverter design. Kesults of Class I Scaling Class I scaling consists of determining the changes in weight, effi- ciency and reliability for the conceptual design of the 3200 cps - 10 KW Static Inverter when it is scaled with respect to reduced power level and to changes in the DC source voltage. The detailed analysis of this Class I scaling is given in Appendix 4-IIL A reduction in the power level requirements from 10KW to ZKW for this inverter reveals that many changes will take place in the inver- ter components. The proposed circuit configuration for the 10KW inverter will remain the same over this output range (10KW to 2KW) requiring no circuit redesign. As the power level is reduced from 10KW the efficiency, size and weight of some components will have a continuous change while certain other components will change in discrete steps. Therefore, those components that must be especially designed for a given inverter such as transformers ancl inductors will have a continuous change in their parameters while components such as transistors and diodes which are not made specifically for a given size inverter will have a step change in their parameters. The weights and losses for the magnetic components in the power stages (output transformer_ AC filter inductors, drive transfor- mers, and delay cores), the semiconductors in the power stages (power transistors, zoner diodes, reactive diodes), AC filter capacitors, and the components in the logic sections are obtained at the lower power levels. These results are plotted in Figures 4-/3/-1 through 4-III-5 for each group of components. The results of these curves in Figures 4-III-1 through 4-III-5 are added together at the various power levels to obtain the total weight and loss for the entire inverter as a function of the inverter rating. These results are shown in Figure 4-ILI-6. Examining the weight and loss curves of this graph (Figure 4-III-6) reveals that a reduction 100 in total loss of 3.88 to 1 (775 watts to 200 watts) and in total weight of 2.51 to 1 (41.5 pounds to 16.5 pounds) will be realized when the total inverter output capacity is reduced from 10KW to 2KW. The reliability of this 3200 cps inverter will remain essen- tially the same over this power range (10KW to 2KW) because its proposed circuit configuration did not change and the same stress levels, duty cycles and de-rating factors can be assigned to these scaled components. The weights and losses for the magnetic components and semicon- ductors of the power stages and for the components in the logic sections were determined at the 10KW power level as the DC input voltage from the source was varied. The power stages were found to be most effected by this scaling of the DC input voltage. When the nominal DC input voltage is lowered below 41 volts, the transistor collector currents become excessive for the 150 amp transistors (STC-2501) that were chosen for this inverter design. Since transistors with larger current capacities are not available at the present time, the 150 amp transistor must be paralleled to provide the necessary current capacity. The output transformer must be modified so that a split transformer technique can be used to balance the current through these paralleled transistors. As the nominal DC input vo!tage is increased above 68 volts, the transistor collector to e_nitter voltages become excessive for the 150 amp - 150 V transistor| (STC-2501) that were chosen for this inverter design. Assuming that these transistors will be available with 200 V collector to emitter voltages, the power stages must be changed to a bridge configuration in order to avoid excessive tran- sistor voltages. The number of power transistors will have doubled while the output transformer size will be reduced. Smaller size power transistors with Large collector to emitter voltage ratings (300 and higher) can be used when the nominal DC input voltage is increased above 90 V because the maximum collector current be- comes less for this 10KW inverter rating. The curves in Figures 4-III-7 through 4-]I[-ii illustrate the changes in the weights and losses for the magnetic components and semi- conductors of the power stages and for the components in the logic sections as the DC input voltage is varied. The results of these curves in Figures 4-III-7 through 4-TTT-1I are added together to obtain the total weight and loss for the entire inverter at 10KW which is depicted in Figure 4-III-12. Examining the weight and loss curves of this graph (Figure 4-III-12) reveals that a reduction 101 in total loss of i. 85 to 1 (1460 watts to 790 watts) and in total weight of i. 38 to i (58 pounds to 42 pounds) will be realized when the DC input voltage from the source is increased from 20 voltsDC to i00 volts DC. The inverter with the lowest weight (40.5 pounds) and the lowest loss (720 watts) is obtained when the nominal DC input voltage is 68 volts or Just before the inverter power stages are changed to a bridge configuration. C. Results of Class II Scaling Class II scaling involves determining the changes in weight, efficien- cy, and reliability for the conceptual design of the 3200 cps - 10KW Static Inverter when it is scaled with respect to harmonic distortion, output phase separation, voltage regulation, and DC input variations. The detailed analysis of this Class II scaling is given in Appendix 4-V. The effects of varying the harmonic distortion specification on the inverter components were investigated with the results that only the AC output filter components - weight, size and loss were effected. The present design specification for harmonic distortion allows for a maximum total harmonic distortion of 5% with each individual har- monic not to exceed 2%. The leakage reactance and winding resis- tance of the output transformer and the phase load impedance are reflected into the AC filters as part of their parameters. The eleventh harmonic which is the predominate harmonic that must be filtered is used to determine the filter component values required for various degrees of harmonic distortion. The harmonic distor- tion before filtering is found in terms of the relative phase shift angle @ (see Figures 4-80 and 4-81) required to maintain the proper load output voltage. The eleventh harmonic has several maxima and minima over this relative phase shift region. The amplitudes and phase angles for the maxima are used to determine the values of the filter components necessary to provide a specified harmonic distortion after filtering. These values of filter components may be used to scale their weights, sizes and losses as a function of allow- able harmonic distortion for the eleventh harmonic at phase shift angles @ of 32.7", 65.5e, 98.2e, 131 e at which the maximum har- monic distortion occurs for this eleventh harmonic. Closing up the tolerances on the total harmonic distortion specifi- cation causes the series filter inductance to increase therefore reducing the capacity of the series filter capacitor in order to maintain exact tuning at the fundamental frequency of 3200 cps. This will cause a decrease in the total AC filter weight and an increase in in its total losses as shown in Figures 4-V-6 and 4-V-7. i02 The following secondary effects will also occur: a) A reduction in the voltage and current feedback sensing cir- cuit filtering may be possible. b) An increase in the AC output filter response time. c) A tighter control on the proper secondary transformer turns ratio must be maintained to suppress the lower harmonics. d) Improving the source and transformer regulation will reduce the size of the filter parameters required since a smaller relative phase shift angle O will be required with a subsequent reduction in the initial total harmonic distortion. Opposite effects on items a, b, and c, can be realized by relaxing the tolerances on the total harmonic distortion specifications. The amount of phase separation between the three AC output phases was investigated in order to determine its effects on the inverter components. The p_sent maximum phase displacement tolerance is two degrees. De-tuning of the AC output filters, variations in the transistor saturation resistance, deviations in the output trans- forn_er leakage reactance and winding resistance, and unsymmetri- cal loading are the factors that effect the phase separation between the three AC output phases. De-tuning of the AC output filters with a full reactive load was found to have the most effect on this phase separation and therefore was investigated. The transistor satura- tion resistance, output transformer leakage reactance and winding resistance, and the phase load impedance are reflected into the AC filters as part of their parameters. Thus the input voltages to the three AC filters can be assumed to be exactly 1Z0" out of phase. The output voltage phase shift on a per-phase basis is then deter- mined with respect to the input voltage as the resultant AC filter resonav0ce cir=uit is de-tuned at the fundamental frequency of 3Z00 cps. A representative range of nominal series filter induc- tots and capacitors at a maximum regulation phase shift angle of 131" were chosen from the Class II Scaling of harmonic distortion outlined in Appendix 4- V, Section A of this report. The initial phase shift angle /___o and gain were calculated first with the AC filters perfectly tuned in order to establish a reference point. The reactive elements composing the series filter branch of one of the phases were then de-tuned to produce both positive and negative reactances whose magnitudes are determined by the percent of de- tuning desired. The AC filters in the other two phases were left 103 tuned at the fundamental frequency to establish a reference point. The amount of relative phase shlft_angle 40< 1% was determined by subtracting the phase shift angle/o( obtained as a function of de- tuning from the reference__ phase shift angle /__o. The relative phase shift angle /t><1% is then plotted as a function of the percent of filter de-tuning for four equivalent series filter component combi- nations as illustrated in Figures 4-V-8 and 4-V-9. The necessary trimming inductors and capacitors can now be found to re-tune this AC filter to the fundamental frequency (3200 cps. ) The weight and loss of these trimming components may then be found as a function of the amount of corrective re-tuning required with the help of the scaling techniques used in Appendix 4-V, Section A of this report. The weights and losses for these trimming components can be added to the weights and losses of the AC filter components to obtain a complete AC filter weight and loss for each phase. The total weights and losses for all three phase AC filters are plotted as a function of the percent output filter de-tuning as shown in Figures 4-V-10 through 4-V-13. The four curves in each of these figures represents the four combinations of series filter inductors and capa- citors that were used. Examining the curves in these figures reveals that the greatest changes in weight and loss contributed by the trim- ming inductors for re-tuning occurs in curve 4 for an equivalent fil- ter inductance of 3ZI_H while curve 1 represents the largest change in weight contributed by the trimming capacitor for an equivalent filter capacitance of 88_fd. Since the losses in the filter capaci- tors were assumed to be negligible, the curves in Figure 4-V-13 willhave constant AC filter losses. The following secondary effects will occur when the permissible relative phase shift tolerance on all three phases is reduced below the present angle of 2 degrees: a) A tighter tolerance will be required for the series filter induc- tots and capacitors as well as the load shunt capacitor for each of t-he three phases for a prescribed harmonic distortion level. b) A more exact tuning between the series filter components for each of the three phases will require some trimming compo- nents which will increase the weight and loss of the AC out- put filters. c) The series filter components may have to be temperature compensated over the required operating temperature range to insure proper matching. 104 d) The output power transformer design will have to be given more careful consideration in order to minimize its leakage reactance and winding resistance and to provide a close balance between its three output phases. e) The power transistors and reactive diodes should be matched for forward voltage drop and saturation resistance. The tolerances requirements on items a through e can be relaxed with the relaxation of the permissible relative phase shift tolerance. The effects of varying the voltage regulation tolerance on the inver- ter components can be directly related to the results obtained for the phase separation study in Appendix 4-V, Section B of tlds report. The present design specification for output voltage regulation allows for a +2 percent tolerance for steady state load conditions with the source voltage held constant. Again, the transistor saturation resis- tance and transformer winding leakage reactance and resistance can be combined with the series elements of the AC filters. De-tuning of the AC filters with a full reactive load was found to be the major factor in contributing to the voltage regulation problem. The same range of AC filter components and load conditions that are used to specify the relative phase shift angle as a function of de-tuning in .Appendix 4-V, Section B of this report are used again. The input voltage to the AC filters was assumed to be fixed. The magnitude of the voltage across the load can then be determined with respect to the input voltage as the resultant AC filter was de-tuned from the fundamental frequency of 3200 cps. For the unloaded conditions, the AC filter output voltage can be considered equal to its input vol- tage for a tuned filter. Therefore, the output regulation as a func- tion of the percent de-tuning for positive and negative reactances can be found for the four representative AC filter component combi- nations as shown in Figures 4-V-14 and 4-V-15. The total 3(_ AC filter weight and loss including trimming inductors and capacitors required for retuning can be related to the permissible percent out- put voltage regulation by relating similar curves in Figures 4-V-10 through 4-V-13 with those in Figures 4-V-14 and 4-V-15. Therefore for a given curve in Figure 4-V-14 or 4-V-15 for positive or nega- tive reactive filter detuning, the percent of output filter de-tuning can be found for a given voltage regulation tolerance. This percent of output filter de-tuning combined with the type of trimming compo- nent required (shunt capacitor or shunt inductor) can be used in Figures 4-V-10 through 4-V-13 to find the total AC filter weight and loss for all three phases. 105 The secondary effects (a) through (e) discussed for the effects on Phase Separation tolerance (Appendix 4-V, Section B) will apply for the effects of varying the voltage regulation tolerance on the inverter components. In addition, the following secondary effects will occur when the permissible voltage regulation tolerance is re- duced below the present value of ±2 percent. a) An increase in the voltage feedback gain will be required with a decrease in voltage regulation tolerance. This may require another differential amplifier stage which will re- quire the following additional parts: Part Quantity Transistors 4 Re s isto rs 5 b) Unsymmetrical loading may place too large a requirement on the averaging type of voltage regulator that is presently proposed. This will require that each phase be independently voltage regulated. The resultant circuit changes for the same 10KW inverter are as follows: 1) Three separate power output flux-adding transformers will be required, one for each phase with an increase in weight of 2.32 pounds_ and in total losses of 55.5 watts using the Orthonol transformer design as reference. 2) The pro-drive reference phase can remain the same. However, three times the power switching transistors and pre-drive circuitry will be required for the flux- adding phase shifting stages. 3) A substantial increase in the complexity of the low level logic will be encountered. Two additional ring counters containing six flip-flops each, two complete phase shift- ing networks, and two differential amplifiers will be required. This will increase the parts count as follows for the above items. Part From To T ransisto rs 8 0 240 Kesisto rs 209 6 27 106 Part From To Diodes 66 198 Capacitors 72 216 Zener Diodes 24 72 The relaxation of the allowable output voltage regulation will eliminate the requirement of a second differential amplifier stage in item a and allow an averaging type voltage regulator to be used with a large reduction in circuit complexity in item b. The present design specification for the DC variations caused by the internal source impedance is +10%, -20% about the nominal voltage of +56 volts. The averaging type of voltage feedback circuit allows the phase shifted stepped waveform to swing from __O _+16" at 44.8 V DC for its full load case to __O f'-90" at 61.6 V DC for its no-load case. If the allowable DC variations on the source is re- duced, then the required corrective phase shift angle will also be less. Therefore_ the number of phase shifting stages can be reduced to a minimum of one for a minimum source regulation of 1.6%. Each phase shifting stage will provide a maximum phase shift of 30 ". A maximum weight reduction of 18.8% for the output transformer can be expected for this reduction in source regulation to i. 6%. The reliability of the phase shifting circuits is improved with the reduc- tion of the source regulation to 1.6% (1% = . 976765/year for three- phase shifting stages to 1%= . 989511 / year fo r one- phase shifting stage). The switching losses for the input voltage regulator that is used to provide the necessary voltage to all the low-level logic circuitry will also be reduced by 17.3% when the source regulation is reduced to 1.6%. If the tolerance on the source regulation is allowed to increase, then its limit is determined by the maximum flux density that the output transformer can support for this particular transformer design. The switching transistorls collector to emitter voltage rating before a bridge configuration is required will also limit the increase in regulation tolerance. The absolute no-load voltage limit appears to be about 70 V before the output transformer has to be redesigned to support this voltage for a bridge configuration required for the present switching transis- tor (150 Vp - 150A power transistors). This increase in the input 107 voltage tolerance to 70 V_ will require no load voltage regulation in the phase shift region _etween 90" and 120". Therefore, four phase shifting stages are required to provide the 0 = to 120" phase shi_t range necessary for a maximum source regulation of 58.4%. A maximum weight increase of 9.2% for the output transformer will occur while the reliability of the phase shifting circuits will be reduced (1% = .976765/year for three-phase shifting stages to 1_ = . 970454/year for four-phase shifting stages) with the increase in the source regulation to 58.4%. The switching losses for the input voltage regulator that is used to provide the necessary vol- tage to all the low-level logic circuitry wilI be increased by 8.69% when the source regulation is increased to 58.4%. I08 III DESIGN OF A 400 CPS PULSE WIDTH MODULATION INVERTER INTRODUCTION Multi-Stepped Waveform techniques and Pulse Width Modulation techniques were both considered for this 400 cps - 10 KW Inverter. The Pulse Width Modulation scheme was selected for this 400 cps - 10 KW Inverter because this approach appeared to offer a substantial weight savings without sac ri- ricing efficiency or reliabt/ity. Examining the various Pulse Width Modu- lation Techniques revealed that classical (not commutated) Pulse Width Modulation with natural sampling would require the least amount of inverter circuit complexity and AC filter weight. Therefore, this approach was chosen so that an optimum trade-off between reliability, efficiency, and weight could be obtained for this 400 cps - 10 KW Inverter. The design of an inverter utilizing classical Pulse Width Modulation with natural sampling can be directed by examining the spectra of the output waveform (Figure 4-98). This spectra represents the maximum amplitude that the carrier frequency and its sidebands as well as their harmonics can obtain relative to the power frequency for a modulation index Iv[ of . 9. The first indication as to direction is the large number of high frequency components in the spectra. If a conventional parallel output stage and transformer is used, a very large hysteresis and eddy current loss com- ponent can be expected. Therefore, the inverter should be a power trans- formerless device in brder to maintain a high operating efficiency. In order to build a transformerless inverter, the input voltage must be high enough to produce a usable output voltage. Therefore, a DC - DC converter must be used at the inverter input. Since the output voltage of the inverter must be alternating, three phase and four wire, the DC - DC converter must be bipolar. The following sections are used to establish this 400 cps - 10 KW Pulse Width Modulation inverter design. PULSE WIDTH MODULATION Certain types of pulse modulation techniques outlined in Section HI-E (High Frequency Techniques of this report) were considered to produce waveforms that would contain a low total harmonic content with relatively simple inverter circuitry. It is the purpose of this section to further explore the various types of pulse width modulated inverter techniques in an effort to determine which method of modulation will produce the least total harmonic distortion. 109 There is a general class of static inverters called "Pulse Width Mo_lulation" inverters. These inverters operate by modulating the width, phase, or frequency of a high frequency carrier signal with a power frequency and then demodulating the resulting waveform to obtain the modulating frequency power. The expected advantages of a system such as this are: 1) Higher efficiency Z) Lower weight 3) Lower harmonic distortion There are several forms this inverter can assume, each form has its advantages and disadvantages. These forms will be discussed here with respect to waveform an_ circuitry. A. Classical Pulse Width Modulation The classical pulse width modulation static inverter is the inverter proposed by A.A. Sorensen in 1960. The inverter output voltage consists of a number of pulse duration modulating pulses having their trailing edge modulated by a power frequency ( see Figure 4-Zl). The analysis of this type of waveforrn is extremely complicated by ordinary methods because of the non-integral relation of the modulating and carrier frequencies. However, by using a double Fourier series, the waveform can be analyzed_ 5 The method developed by W. K. Bennett and explained by H. S. Black 1 is" a very useful explanation of the double Fourier series analysis technique. Blackts treatment of the subject yields two equations describing the spectra of a pulse width modulating waveform_ one for natural sampling and one for uniform s a mpling. a) Uniform Sampling The difference between natural and uniform sampling is quite subtle and undetectable by visual examination of the resulting waveform, but is readily seen by examining the spectra of the waveforms. Basically, uniform sampling is the modulating technique whereby the pulse width is proportional to the instan- taneous value of the modulating wave at uniformly spaced sampling times. This is shown in Figure 4-99. The top waveform is the 15 "Modulation Theory" Harold S. Black , D. Van Nostrand Company, Inc., 1953, by 110 15 modulating signal. Superimposed on the modulating signal are lines representing uniform sampling times. Superimposed on this waveform is the resulting pulse amplitude modulated wave- form representing the value of the modulating signal at the uniform sampling times. Added to this waveform is the sweep _¢ave from the synchronizer from which the pulse width modulated waveform is obtained. The width of the resulting pulse is equal to the width of the summed sweep and PAM wave when intersected by the control value. A typical block diagram of a Uniform Sampling PWM Inverter is shown in Figure 4-100. The spectra of a pulse width modulating waveform employing uniform sampling can be expressed by the following equation which is a modification of an equation by Black 15. Z (nTFMF (t) = [_Jc sin (n_vt n77-_v _ n'_- ) n=l n "TT[_Jv L_) c 2 L)o n--I _4_ c sinrn _ct-jo(m'[7"M)sin(m LJct-M]-[ ) mTr (4-32) where + n= 1 n=± 1 sin (mh)c+n_v) -[]" UJc M is the modulation index, which is defined as the amount of excursion of the trailing edges of the modulated pulses. M cos t_]v is the modulating wave. and _c is the carrier wave angular frequency. op. cit. 111 In order to get the maximum value for the modulating wave com- ponent, a modulation index of I. 0 will be used. This is contrary to usual practices in communications but expedient for power con- version. A spectrum representing the above equation is shown in Figure (4-I01). A ratio of 25 to one was used for the carrier to modulating signal ratio. If the modulation is decreased from a value of I. 0, the fundamental component decreases and the carrier frequency amplitude increases. The unwarranted increase makes it more difficult to filter the output. The spectrum shows the fundamental (_]v) component having a relative value of one. The carrier and its harmonics and sldebands are seen to diminish rapidly and a filter that cuts off at about 15[A]v will completely eliminate these components. An undesirable aspect of this type of modulation (uniform) is seen by the presence of second, third, fourth, fifth, and sixth harmonics of[Air. These harmonics are quite close to_-_Jv and will require a rather large and heavy filter to eliminate them. The method of uniform sampling has the undesirable property of producing unwanted and hard to remove harmonics. The sampling method which does not produce these fundamental harmonics is natural sampling which will be discussed next. b) Natural Sampling Figure 4-102 illustrates the natural sampling method for modulating the width of a train of pulses. It can be seen that the pulse width is a function of the average value of the modalating waveform during the sampling interval and not the value of the waveform at the instant of sampling. A block diagram of a naturally sampled PWM inverter is shown in Figure 4-103. The expression for the spectra o_ a naturally sampled pulse width modulation is (from Blac_; 15 M F(t) = -_- cos _XJvt + sin m_Jct (4-33) _o m-i m 77" _ _ jo(m'[T M) sin (reLict - re'iT ) A___ m'[7" m=l (continued on next page) 15 op. cit. llZ (continued from previous page) Be nffi_ DO _ > j n(m=_M)mT_ m= 1 n=il sin (m(_ct + n[_rt - m-_-- n 7"[ ) 2 where M is the modulation index M cosCJvt is the modulating voltage is the carrier angular frequency The spectra is shown in Figure 4-104. (LJc = 25_v for sample calculation. ) It is seen that natural sampling yields a spectra identical to the spectra for uniform sampling with the exception of harmonics of the modulation frequency. The naturally sampled waveform is free of lower harmonics (2Ldv, 3t_/v, 4L_/v, etc) and the lowest _armonihs are sideSands of the c_rrier frequency. The above discussion makes a very good case for natural sampling as the type to use for a static inverter since the filtering problem is considerably lessened when compared to the uniform sampling method. Another type of output voltage that is beginning to gain popularity is a form of pulse width modulation which produces pulses that are commutated, The pulses appear in bunches having a square wave envelope. The next paragraphs will examine this waveform. Commutated Pulse Width Modulation The commutated pulse width modulated waveform is shown in Figure 4-105. It is obtained by first rectifying the modulating wave as shown in the top waveforms of the figure. This waveform is then operated on by the modulator as before. The resulting pulse width modulated waveform is then commutated by a square wave which is in synchronism with the modulating waveform. The resulting commutated waveform is shown at the bottom of the figure. A block diagram for Uniform Sampling - Commutated PWM inverter is illustrated in Figure 4-106. 113 III The analysis of this waveform is exceedingly difficult. A triple Fourier series expansion can be used to analyze the waveform where the three functions of time are the rectified modulating wave, the sweep wave and the commutating signal. However, the expressions for the modulating wave and the commutation wave make the triple Fourier series extremely complicated. A simple method of analysis, while not as accurate, has been used to analyze the waveform. The method of analysis used was to break the waveform down into a number of simple quasi-square waves, each having an on-time equal to the width of an individual pulse in the waveform. Each quasi- square was then given a phase-shift and analyzed. The harmonic components of like frequency in all the quasi-square waves were then summed. The result was a number of harmonics of various amplitudes and is shown on the spectra of the waveform seen in Figure 4-107. The commutated waveform spectra reveals that a large number of undesirable harmonics are present; namely, the thirdjfifth, seventh and eleventh. These harmonics are the result of the sampling method used (uniform) and will diminish if natural sampling is used. It ia important to notice that the spectrum of this waveform is nearly identical to the classical pulse width modulated waveform and is clearly no improvement of that waveform. The choice of waveform to be used by an inverter can be decided by comparing the circuit complexity required for each method (classical or commutated). Each inverter requires a dc-dc converter if a high voltage DC input is not available, a logic stage, a power inversion stage, and an output filter. Regulation is accomplished for each inverter by either controlling the index of modulation M, by incorpora- ting regulation in the DC - DC converter, or using some type of AC regulator. However, the commutated waveform inverter will require a commutator or demodulator stage and its associated logic circuitry. The size and weight of this additional circuitry will more than offset the reduction in output filter size and weight that will be obtained for this commutated waveform inverter. Additional inverter power loss will also be contributed by this demodulator. Therefore, the classical Pulse Width Modulation approach with natural sampling is best by virtue of simplicity. GENERAL DESCRIPTION The block diagram of the complete inverter is shown in Figure 4-108. The three phase square wave reference generator produces the low fre- quency (400 cps) modulating signal. These three signals are displaced 1Z0 degrees with respect to each other to establish the three phase 114 relationship of the output voltage. The reference waves are then passed through controllable attenuators which have a normal attenuation of zero, but when an overload current is detected at an output line, the proper attenuator is activated to attenuate the size of the modulating signal which in turn reduces the voltage of the overloaded line. After passing through the attenuator, the fundamental frequency of the output square wave is extracted by the tuned amplifier which has a unity voltage gain at 400 cps. The p_rity of this resulting sinewave is as high as practical because it determines the waveshapes of the output voltage. The modulating sine- waves are then mixed with the sweep wave in the three summing networks. The resulting waveform is a sinusoidally undulating sawtooth wave which is then sent to the slicer circuit. The slicer circuit is an absolute level detecting system that produces pulses having a width proportional to the modulating signal level during the sampling interval. The sampling interval is determined by the sweep wave generator which produces a sawtooth sweep wave at the carrier frequency. The variable pulse width signal is then amplified and sent to the driver stage which transforms this signal into a form suitable for use by the power stages. The power stages convert the low level drive signals into the required high power level output. The power source for the power stage is the regulated DC - DC input converter. The input converter raises the input voltage to the reqhired voltage level for use by the power stages. The high power output voltage of the inverter is then filtered to eliminate the carrier and its sidebands from the output voltage leaving only the power frequency voltage. The voltage regulator and reference develops an error signal which is fed back to the input regulator to maintain a constant output voltage. Also present at the output lines are three current transformers which detect any overload currents and act on the modulating signal via the current limit and reference circuit to reduce the power frequency output voltage thereby limiting the overload current. The individual blocks will be discussed in more detail in the following sections. IV POWER STAGE The circuit of the power stage for the PWM inverter is shown in Figure 4-109. The voltage waveshapes at various points in the power stage are shown in Figure 4-111. Waveshape (a} illustrates the inverter output voltage before filtering. This is a pulse width modulated waveshape that is naturally sampled (see "Pulse Width Modulation" -Section II-A-B of this report} and has a modulation index M less than one. A perfect inverter can have a modu/ation index M of one but this implies an infinitely narrow pulse width at extremes of the modulating waveform. While this is desirable, since it produces the maximum output voltage, it is impossible to produce in practice because of transistor switching speed limitations. 115 A modulation index M of 0.9 produces a minimum pulse width of 10 microseconds which can be reasonably reproduced by a transistor which switches in one microsecond. The input voltage required to produce rated output voltage in the power inverter is a function of the modulation index M and the filter efficiency at the power frequency (400 cps). In our case, the modulation index M is 0.9 and a 5% voltage drop can be expected in the filter at full load. With this information, the input voltage can be determined. The 400 cycle component before the filter is: E = 115 (1 + 0.05) = lZl volts rms1 since V (input voltage) V-- V = 121 V2 M e_.l_l where e 1 = _-2E M = 190 volts The voltage across one of the half phases is shown in waveform (b) of Figure 4-111. This voltage has a magnitude of 2V or VCEma x = Z x 190 = 380 volts. This rather high voltage can be effectively switched by one high voltage transistor. An KCA developmental type TA Zll0 has a VC_ X of 400 volts with a V of 8 volts. However, this voltage rating is too_ow when a E voltage s_a_ety factor is considered. A 400 volt transistor permits only 20 volts or a 5% safety factor. This situation is improved by using two transistors in series which yields a safety factor of 800/380 or Zll%. The next problem to be solved is to equally divide the supply voltage across the power transistors when they are in the "off" condition. Due to the possibility of unequal ICE x currents (ICE X is the collector leakage current when the base emitter junction is reverse biased) in the two series transis- tors, the effective resistive equivalent of the two transistors may vary widely and cause an unequal voltage distribution across them. Any voltage unbalance automatically reduces the safety factor. In order to reduce the possibility of voltage unbalance, a voltage divider resistor (Kd) is included in parallel with each transistor. The value of the divider resistor is a function of the maximum unbalance in ICE X in the power transistors and the maximtu_a tolerable voltage 116 unbalance allowed between the two "off" transistors. In order to determine what size Rd should be the series power transistors can be thought of as resistors having a resistance equal to VCE divided by the leakage current ICEX. R = VCE (4-34) ICEX The value of R will vary from transistor to transistor because of the spread of ICE X- This spread will produce two values of R,- a maximum and a mlnlmurn value, i_%rnely-t_ and R respectively, The ratio of RM to R is called (a). M m rn (4-35)RM = a R m An equivalent circuit can be drawn of the series transistors and divider resistors combination and is shown on Figure 4-112. The equation for the circuit is: E RdRM ) R dR--_-m)]I --.-_M + ( = V Let k equal a voltage unbalance factor such that: I ( RdRM ) = I k( RdRm ) Rd+ R M Rd+ R m (4-36) (4-37) cancelling I and solving for Rd; Rd = RMR m (k-l) ( RM-k R m) But since R = a R the equation becomes: M m a Rm(k- I) R d = (a-k) (4-38) (4-39) The values of R d are plotted in Figure 4-112 for values of (a) from 2 to Z0 and for values of k from 1.1 to 2. 4. 117 From the graph of R d on Figure 4-112, it can be seen R dvaries from0. 1 R m toOoR m. This is a very large range, but it can be narrowed by limiting the maximum voltage across any transistor to twice the voltage across its series partner which determines a value of k equal to two (2. 0)° (A value of k equal to 2.0 yields a safety factor of 150_0.) Also, since a very large number of transistors are to be used, it should be a simple matter to arrange them in groups of two which have a maximum K1V[ to R m ratio of 10. With these restrictions (k=2.0 or less and a =10 or less) a value K d can be found from the graph which is 1.25 K . ' m Since we are using a TA 2110 transistor which has a ICE x maximum of 10 ma. at 400 volts (R m = 400 = 40 K), then R d is equalto 1.25 R m or 50 Kilohm s. 10--0c2" The power rating of the resistor is equal to the maximum voltage across any divider resistor squared divided by R d or Z p = E (4-40) R d k where E = ( .---_-.) V (4-41) K+I therefore P = (k--_l)2 vZ (4-4Z) R d in our case P = 2 (380) z = I. 28 watts 50 x 103 (4-43) The voltage divider resistors R d will be of the wire wound type whose temperature coefficient will be matched as close as possible to that of the power transistors in order to minimize the change in voltage balances as the ambient temperature changes. During the time when the power transis- tors are turning "off", the voltage dividing resistors are useless because the turn-off or fall times of the two series connected transistors are net exactly equal. The unequal fall times cause a situa_on in which the full supply voltage is developed across the fastest transistor to turn off. In order to " prevent damage to the transistor by these unwanted voltage transients, a zener diode clarnp with a value of less then VCE X and greater than 2V is 8hunted across each transistor. In our case a zener diode rated between 380 and 400 volts is required. A diode with a value of 395 volts can be easily obtained by a series connection of two standard zener diodes. The current 118 rating of the zener diode should be at least ten times ICEXmax in order to provide maximum effectiveness which means the zener diodes must have a power rating of about Z0 watts each. The nearest zener diode rating to Z0 watts is 50 watts which will provide a good safety margin. The current rating of the TA Zll0 power transistor is 10 amperes while the rated load current is: IL = 10 KW = 41.4 amps • 7PFx l15V x 3 phases The peak current is: leak = _x 41.4 = 58.6 arnps The waveshape of the transistor power switch current is shown in Figure 4-111 for unity power factor load. With overload and short circuit considerations, the power switch current may be as high as 250 percent rated current or a maximum current of: I = 2.5 x 58.6 = 147 amps In In order to switch this large amount of current at least fifteen power transistors must be connected in parallel in each half phase using a closed chain balancing reactor system. The power stage circuit complexity can be reduced by reducing the number of paralleled transistor switch legs required if larger current capacity power transistors with compatible switching times and VCE voltage ratings can be found. The balancing reactors assure the equal distribution of current between the paralleled transistor s. The balancing reactors must be designed to support V o per coil at a current of 10 amperes and a frequency of 10 kilocycles. V o is the total unbalance voltage that may be presented by the transistor switches and is equal to difference between the maximum and minimum saturation voltage of the series connected transistors or Vo = (Z VCEma x -Z VCErnln ) (4-44) 119 The coefficient Z is used because two transistors are connected in series. The maximum and minimum saturation voltage for the type TA 2110 power transistor is: IC VCE sat max VCE sat rain I0 amp I. 0 volts 0.6 volts The voltage V ° that the balancing reactor must support is equal to: V o = (Zx 1.0) - (Zx.6) = 0.8 volts The wire for the balancing reactor must have a cross section of 5,000 circular mils based on a 500 c.m. per amp rating. A number twelve conductor will be quite sufficient (5184 c.m. ). Since the operating frequency is quite high and the supporting voltage of the coil (Vo) is quite low, a very small core may be used. In order to determine the core size (cross sectional area) the number of turns is fixed first. In this case assume that each coil will have three turns. The required core area can then be determined if the maximum flux density is known. Assume here that Hy Mu 80 is used which has a B max of 7 KG. Therefore, from the equation N ----" VoX 108 From Quarterly Report No. 2, page 107 2 BmfA of the "Optimization Study of High Power (4-45) Static Inverters and Converters" -NASA- CR-54021) The required area is N V o x 108 ZBmFA (4-46) where A .. V o = B m = the core area in square centimeters the unbalance voltage maximum flux density in Gauss frequency of Operation in cycles per second number of turns per coil. Therefore A = 0.8 x 108 ZxTx 103x 104x3 = 0.191 sq. cm. IZ0 or .A = 0. 191 = (2. 54)'z O. 0296 square inches A suitable lamination to use for the core is the 34-E size which has an outside dimension of 0.75 x 0.82 inches and a center leg width _f 0. 249 inches. If. 014 in. thick laminations are used, a total of 9 laminations will provide the required cross sectional area. The weight of 9 lamina- tions is 0. 0199 pounds. The resulting core loss is about 1 watt per pound or about 0.02 watts per core. The copper weight is about 15 gins or . 03B pounds and will be practically lossless. The total weight of the reactor will be . 053 pounds and have a constant loss of o 02 watts. Figure 4-113 shows this reactor. In order to prevent reverse current from flowing through the power transistors, a blocking diode is connected in series with each half phase. When the blocking diode is in the circuit the reactive current has no path so a reactive current diode is placed across each half phase. The current through the reactive diode is shown in waveshape (d) of Figure 4-111. The rating of the blocking diode and the reactive diode is determined by the maximum rms current that they are required to conduct. The b!ocking diode is required to conduct almost a complete half cycle of current which has a full cycle rms magnitude of 104 amps for the 250% overload case. This means the rating of the blocking diode is one half the maximum peak current or Irating = 1/2 /'_ 104 73.6 arnps (average over one cycle of 400 cps. ) Another characteristic which must also be considered when choosing a blocking diode is the recovery or commutation time. Most rectifiers have a construction directed toward low forward drop and current handling ability and are quite efficient at 60 to 400 cps operation. When _perated at frequencies such as those encountered in this inverter they become quite inefficient. The inefficiency is due to the rather long commutation time required to return the diode to its blocking state, this time usually runs from 1 to 5 microseconds. In order to overcome this difficulty a fast recovery type diode must be used. Diodes are available that recover their blocking state less than 200 nanoseconds. The only difficulty with these diodes is the low current handling ability. At present, the maximum current rating of fast recovery diodes is 30 amps. 121 Paralleling of the 30 amp rectifiers is necessary to meet the 73.6 amp required ratin Z. This is accomplished by dividing the paralleled power transistors in each half phase into groups of three and connecting one 30 amp fast recovery diode to each group. Wlth this technique, the balancing reactors used for dividing the current equally among the power transistors also divides the current equally through the blocking diodes. This arrangement is shown in Figure 4-109. The reactive current diodes must also be of the fast recovery type because of the very high operating frequency. The rating of the reactive diode is about 30 amps. This rating can be met with one rectifier. A. Power Stage Efficiency The power stage efficiency will be calculated here for half load, full load, and twice rated load. (The power factor of the load is 0.7. ) The losses will be classified into three categories; "on" losses, "off" losses, and switching losses. The items that dissipate power are power transistors, balancing reactors, blocking diodes, reactive current diodes, base-drive resistors, and the divider resistors. The first item of power loss calculated will be the transistor "on" losses. The current waveform through the power transistors is shown in (c) of Figure 4-114. The rrns value of the current is where I L I = 1 I xM rms _ L = rms loa_d current (4-47) M = index of modulation The "on" losses in the transistors are where Pton Rsat_eq" = 2Rsat 15 Z = (Irms) Rsat - eq (4-48) where Rsat K sat-eq. = saturation resistance of one power transistor = Equivalent saturation resistance of the series- parallel combination of 30 transistors. IZ2 therefore P ton 1 M_j Z = (_ I Rsat (transistor "n" losses)L 15 (4-49) In our case, the factor M and Rsa t remain constant so the transistor "on" losses can be tabulated as follows. (It must be remembered that this table and others llke it are the losses computed for one half phase containing 30 series - parallel transistor combinat-_ons• The total power losses will be collected later• ) TABLE 4-10 IL 2 2Rsat $ Amps IM ( _ IL M) 15 Pt-on-watts Half rated load Z0. 7 .9 173 Full rated load 41.4 ,9 693 Twice rated load 8Z. 8 •9 Z775 Maximum R-sat for TA Zll0 is 0.1/t. •0133 2, 3 •0133 9. Z4 .0133 36.9 The transistor "off' losses will now be calculated. This loss will be calculated together with the divider resistor loss because of their intimate relationship in a four element network. Previous calculations determined an equivalent resistance for the transistors of 400 K and 40 K (maximum difference assumed) and a divider resistor value of 50 K. The equivalent two terminal network has a resistance of: R = rRdRrn ) + ( RdRM )_ J where Rm_Rd divider resistance 1 15 (4-50) minimum tr sistor resistance maximum transistor resistance number of paralleled combinations R R I(50x103x40x103) = L50x103+ 40xi03 ) = 4.45xI03___ + (5o o3x4oOxlO3j 123 The transistor-dlvlder resistor "off" losses remain constant regardless of the inverter load. P -off = (2V) z (4-51) t-Rd Pt_Rd-off = (380) 2 = 32.4 watts 4. 45xi03 The transistor - divider resistor "off" losses (Pt_Rd_off) are computed for each half phase containing 30 series - parallel transistor combinations. The total transistor - divider resistor "off" losses will be collected later. The power loss in the blocking diode is proportional to the load current and is _l_ ILM) Vd (4-52)PBD = (_-2 where V d = the diode voltage drop Vd = 1 volt TABLE 4-11 Half rated load Full rated load Twice rated load PB-D-watts 13.17 26.4 52.7 The power loss in the balancing reactors is principally core loss and this will remain constant over the load range. Previous calculations have indicated a power loss of .02 watt per reactor. The total balancing reactor loss is: p = 15 x . 0Z = .30 watts BR The reactive current diodes conduct only during the spaces between the power switch pulses. The current they conduct is approximately I .. (Z Vc_ ILM , PRD = VdI (4-53) 124 TABLE 4-1Z I-amps _'RD - watts Half rated load Full rated load Twice rated load 6.57 6.57 13. 14 13. 14 Z6. Z8 Z6. Z8 The only remaining semiconductors are the zener diodes. During normal operation of the inverter, these diodes should not conduct for more than 1/Z microsecond. This conduction occurs during the switching transient that occurs at the rise and fall time of each power pulse or at a Z0 KC rate. The current should be less than 100 milliamps. The power dissipated by the zeners is: P ZD where f = t = I z Y z = N = = x-_-'t"txlxVz ) N (4-54) rep rate of transient length of transient current zener voltage number of zeners per half phase. 3 PZD = Z0xl0 x. 5x10-6x. 100xZ00x60 _, IZ watts The rather low average power dissipation of the zener diodes infers that small zener diodes may be used. This is not the fact, however, because the zener must be able to support rather high instantaneous power pulses. It is this rather high p_wer pulse that raised the power level of the zener diodes to fifty watts each. Probably the best way to size the zener diode rating is to build the circuit and measure the actual transient current for a number of cases and rate the zener according to the highest current pulse detected. The switching losses in the power transistors will be calculated next. Because of the continuously varying magnitude of collector current that must be switched, a discreet calculation for each switching instant must be made. The transistor switching power loss may be expressed as follows: 125 ts P t-s eldt (4-55) where T = period of power cycle (__1_1.) f V e = transistor voltage during switching i = transistor current during switching ts --" length of transistor switching transient for either "rise" or "fall" times. The switching transient of current and voltage are assumed to be linear functions with respect to time. The voltage transient e is: Ee = VCE max 1 ts where VCE max = maximum collector voltage (4-56) t = incremental switching transient time The current i during the switching transient is: ts (4-57) Where _ is the percent of peak load current _-Z I L at the instant of switching. The switching power dissipation per switching instant may be expressed as; ts Pt-s --_ which becomes (4-58) Pt-s- Voi_._ tsX (4-59) 6T 126 The total transistor switching power for n switching instants per power cycle may be expressed as: k =n k=l k=n where the Z _ ts represents k=l the summation of the percentage of peak load current times the transistor "rise" and "fail" times. These products are determined alternately and then summed. Because an arbitrary value of voltage unbalance of two was chosen for the voltage division across the two series transistors, two power calculations were made for each load current value. The values of Pt-s are tabulated bzlow. TABLE 4-13 Half Rated Rated Twice Rated Load Load Load Pt_s I 6.53 watts 13.06 watts 26. 12 watts p 2 t-s 3. Z6 watts 6.52 watts 13.04 watts P 9.79 watts t-s Total watts 19.58 watts 39. 16 watts The transistor base drive requirements are I. 7 VBE max at one amp. A three volt output will b_ supplied from each secondary drive winding. The base drive resistor required for each transistor is I. 3 ohms with a I0 watt dissipation capacity. The total base drive loss per transistor circuit is 3 watts and is 90 watts loss per half phase. The total base drive loss per transistor circuit will remain constant independent of the transistor load because it is a constant voltage base drive scheme. 127 B. Power S+.age Weight Breakdown The following is a list of the PWM static inverter power stage parts• The part quantity and weight are listed to provide a total parts weight and count• There may be a certain degree of inaccuracy in the total weight due to certain unknowns. The unknowns are items like the weight of terminals required on the balancing reactors or the weigh +. of the insulation required on this component. Item Power Transistors - Type TA 2110 180 Zener Diodes - Type 1N3350 360 Reverse Blocking Diode Type 1N3918 18 Reactive Current Diode Type IN3918 6 Balancing Reactors 90 Divider Resistor - 50K- 10W 180 Base Drive Resistor- I.3/I. -10W Drive Transformer TABLE 4-14 Quan Wt. Ea. Total Wt. 0. 143 ib 25.8 Ib •0264 9.52 •03125 0. 562 •03125 0. 187 •053 4. 770 •0125 2. 25 180 .0125 Z. 25 45 .ZZ 9.9 1059 parts 55. 239 ib 128 Total Power Stage Losses: Dis sipating Item Half Rated Load Transistor "on" losses 13.8 Transistor* * "off" losses 194. 4 Transistor Switching Losses 58.8 Transistor Base Drive Losses 540 Blocking Diode Losses 79 Reactive Diode Loss 39.4 Zener Diode Loss 7Z Balancing Reactors I. 80 Total Watts Loss 999.2 W Power Output 5000 W Power Stage_ Efficiency 83° 34% Pout • Efficiency = ( TABLE 4-15 Rated Load Twice Rated Load 55.4 221.5 194.4 194.4 117.6 Z35. Z 540 540 158 316 78.8 157.6 7Z 72 I. 80 1218.0 W I0000 W 1.80 1738.5 W Z0000 W 89.14% 9z.o% Pout+ Plos s ) x I00 (4-60) Transistor "off" losses are composed of leakage losses and divider resistor losses. 129 V DC-DC CONVERTER STUDY A. Introduction While many of the problem areas associated with inverters are also found in the design of DC-DC converters, there are many aspects in which they differ. Hence, a separate study of converters is worth- while. Converters come in many different configurations as can readily be appreciated. Some are used to convert to DC at a higher potential than the primary source, and some are used to convert to a lower potential. Many have only one output voltage, while others provide many different outputs. The power handled varies over wide ranges. It follows, therefore, that the choice of a particular conversion method and the optimization of it depends on the application. For the purpose of this study, it has been decided to concentrate on a converter which could be used in the Pulse Width Modulation scheme decided in Section II - "Pulse Width Modulation" of this report. This means we are directing the effort toward the design of a converter which has two outputs, both having the same potential and power ratings, although one voltage is positive, with respect to ground, while the other is negative. The total required output power is slightly in excess of I0 KW. Inasmuch as our specification dictates a substantial step-up in voltage, the use of a transformer switching stage is indicated. Because of the high power involved, and the necessity of providing well regulated and well filtered power, systems utilizing other than push-pull outputs were disregarded. Those systems which were considered worthy of study are discussed next. B. Inversion Methods While most inversion modes use basically square wave generation for high efficiency operation, a number of modifications are possible in order to provide regulation. These methods unfortunately, in general, provide voltage regulation capability only at the expense of a need for more filtering and less efficient utilization of switches and transformers. Since our requirement is for two separate outputs, both producing the same magnitude of voltage, it was felt that the use of two separate output regulators would add unnecessary complexity to the system. 130 This leaves us with the choice of using either inherent regulation in the conversion stage or an input regulator. Methods which were considered were: 1) Pure Square Wave Generation with external regulation Z) Ouasi-Square Wave Generation using a) One Power Stage b) Two Phase Shifted Power Stages a) Pure Square Wave Generation with External Regulation This method of conversion has much *.o recommend it. It utilizes two power switch elements connected in a push-pull configuratioa, and generates pure square waves, which are transformed to the power output voltage and then rectified and filtered. Because the rectifier operates on pure square waves, very little filtering is necessary. However, voltage regulation must be provided by amplitude modulation through control of the DC input to this stage. This control can be provided by a switching type of regulator. Two variants are possible: 1) the use of a "Morgan" chopper or similar circuit, or Z) the use of a pulse width modulated rider on top of the DC battery voltage. Both of these systems are usable here because no restraint is placed on their output voltage, other than what is reasonable from the standpoint of the power switch voltage specifications. Obviously, too low an output voltage requires that larger currents be handled. b) Quasi-Square Wave Generation Whereas the previous method had no inherent regulation capability, the generation of quasi-square waves does provide this function. Two different methods of generating these waves are possible. First, the conduction time of the power switches can be controlled, so that quasi-square waves rather than pure square waves are generated. Alternatively, two stages, both generating pure squares, can be used. By pha3e shifting one with respect to the other, and adding their outputs, quasi-square waves can also be formed. 131 The use of two stages is preferable for two reasons.: (1) since high power is being handled, paralleling of transistors will probably be required. The necessity of using a minimum of four transistors in this system is thus not a serious drawback, in fact it may be considered to be beneficial since this system yields extra benefits other than simple higher power capability: (2) two of the four power switches are always "on" - there never is a period when the transformer looks like a high impedance. This is highly desirable, especially since our load is not a pure re sistance. c) Selection of a System Because we are somewhat limited in frequency due to the necessity of using high current devices, it behooves us to select a system which uses a minimum number of magnetic components. The pure square wave system with pulse width modulated riders has a distinct advantage in this respect. The output filter can be very small since pure square waves are being rectified, and the switching stage used to control the DC input to this stage need handle only the "boost" power, i.e. the power needed to raise the battery voltage up to its maximum. It follows, therefore, that at the high battery input voltage the switch handles no power, while the maximum power it handles is at the low battery condition. All of the other systems handle full power regardless of the input voltage. This means that the transformer used in the switching section can be smaller for the boost system than for the other approaches. Both of these factors contribute to a lower overall system weight, so this _vas the type of regulator selected. C. Weight and Efficiency Versus Frequency Tradeoffs One of the major problems confronting the designer in DC to DC converters is the selection of an operating frequency. It is a problem since it has such a major effect on losses and weight. Barring other restraints, the selection will normally be a high frequency for low magnetic component weight or a low frequency for low transistor switching losses and low transformer losses; hence high efficiency, or a medium frequency as a compromise. Since we are confronted with the problem of handling high power, our selection of a switching transistor is somewhat limited unless large 132 scale paralleling is used. The use of a high current transistor rather limits the choice of frequency, since they are restricted in their switching speed. For this reason, a frequency of one kilocycle was arbitrarily picked as the operating frequency. This appears to represent a reasonable compromise between extremely low weight and very high efficiencies. A more detailed analysis will b_ required to determine the most optimum operating frequency in regards to weight, reliability, and efficiency tradeoffs. D. Detailed Design The complete regulator design is shown in Figures 4-115 and 4-116. A parts list is Included, showing representative values (Figure 4-117). a) Power Stage To step up the regulated DC voltage to the desired _Z00 V DCs a push-pull stage comprising transistors O3a - Q3b - Q4a and Q4b and transformer T Z is used. This stage generates pure square waves at a frequency on 1 KC. Zener diodes DS, D6, D 7 and D 8 are used to protect the transistors against overvoltages. Because of the high currents being switched, it was necessary to parallel two transistors per switch. Silicon Transistor Corp. type 2501 transistors will be used and balancing reactors (T B and T4} will be provided to force current sharing. b) Rectifier - Filter The rectifier circuit comprising diodes Dg-D Io"^-D,_ and DI_L converts the generated square waves to DCo In actuality w_ile this rectifier resembles a bridge circuit, it actually operates as two full wave circuits in tandem. One produces the positive output, and the other the negative. This turns out to b_ a very efficient usage of the transformer. The filter consists of a very small filter choke (L2} and capacitors C 4 and C 5. Resistors R12 and R13 are bleeders. c) Input Regulator To amplitude modulate the square wave power circuit a DC input regulator is used. 133 This circuit, comprised of controlled rectifiers, SCR 1 and SCRz_ transistors Q1 and QZ' transformer T. and filter and C_ o.ks by p l e'son of voltage. These pulses are actually parts of pure square waves being generated by transistors Q and QZ" The pulse width is modulated by controlling th% firing point of the two SCR's. At maximum battery voltage the SCR's will not conduct at all, so the DC current flows from the battery through diode D_ to the output. At a battery potential less than maximum but {reater than minimum, the DC current will flow along this same path until the SCR is fired sometime during the square wave half cycle. The initiation of SCR conduction automatically commutates the diode D 3 and a higher voltage "pulse" is added to the battery potential through the SCR. The SCR's are themselves automati- cally commutated by the reversal of voltage from the transformer. By using the SCR's from an AC source, the need for external commutating circuitry is avoided. The RC network shuntin_ the SCRis are used to alleviate dv/dt problems since we are operating at a moderately high frequency and using square waves. The SCK's should also be selected for high dr/dr capability. The transistors Q1 and QZ form a square wave push-pull generator. It should be noted that this stage provides only the boost power, that is, the difference between the minimum and maximum battery voltage. The closer these two figures are to each other, the less power this stage has to handle. Zener diodes D and D z act as overvoltage surpressors to protect the transistors 1. The output filter of the regulator is comprised of choke L. and capacitor C 3. Note that since the "raw" input voltage to t_e filter does not have the large voltage swing which is common to most types of switching regulators, that the required filter elements are small. Diode D 4 acts as a free-wheeling diode. Resistor R 3 is a bleeder on the filter. d) Oscillator and Driver A Jensen type two core square wave oscillator is used as the basic frequency reference. Frequency is held to within _5°_o by the zener voltage regulator on the DC input to this stage. Power is taken from this stage to drive both the transistorized output and regulator stages, and also to provide drive for the magnetic amplifier MA-1. This mag amp is used to control the 134 firing angle of the SCKIs in the regulator. The positive output voltage of the DC-DC converter is returned to the control winding of the SCR control magamp MA-1. When the battery voltage is high, the current in the control winding reduces the magamp conduction angle which in turn reduces the SCR firing angles. When the battery voltage becomes low, the current in the control winding increases the magampts conduction angle which in turn increases the SCR firing angles. The amount of feedback control is determined by the ampere-turns that is set by potentiometer RZ4 on the bias winding. To provide fast rising gate drive waveforms for these SCRIs SShockley diodes DI8 and DZI are used as fast switching wave shaping devices. The output voltage from this circuitry is stepped down to the required gate voltages by transformer T 7. Fast rising gate waveforms are necessary if excessive S_R power loss is to be avoided. Because the frequency tolerance is not hypercritical, it is not expected that any buffering of the oscillator will be needed. This can be provided if it proves necessary, however. e) Input Filter Since this regulator is basically a switching type system, an input filter will undoubtedly be required. A simple Pi type should be s ufficient. E. Expected Weights and Losses Transformer T 1 Transformer T Z Diodes D9--_ D12 Balancing Reactor s SCR - SCR 1 Z Choke L 1 TABLE 4-16 Weight 13.0 Z6.9 0.5 0.5 0.5 2.4 Losses 66.4 124. 1 60.2 26.0 200.0 80. 0 135 TABLE 4- 16 (continued) Transistors QI QZ Transistors Q3a' Q3b' Weight 0.5 Q4a' Q4b' 1.0 Miscellaneous 5.0 TOTAL 50.3 Ibs 278.4 50.0 101Z. 0 watts VI LOGIC A. Efficiency = i0,700/i0,700 + = 91.4_/o 101Z P. 4 KC Clock The Z. 4 KC Clock is a multivibrator oscillator (Figure 4-118 and 4-119) that runs at six times the output frequency of the inverter or Z. 4 KC. This clock triggers the three phase square wave oscillator which divides the clock frequency by six to yield the required 400 cps control signal. The frequency accuracy of the clock will be main- tained at _0.5 percent over a temperature range of -55"C to +85"C without an oven. Also, any variation in input voltage (15V) up to :kZ0% will not change the frequency accuracy or stability. The good stability is obtained by clamping the collector voltage of transistors Q67 and Q68 with the zener diode D58 and also clamping the timing RC network supply voltage. Temperature compensation is obtained by virtue of the fact that the diodes D48, D60 and D58 have tempera- ture coefficients that cancel over the temperature range. The output voltage of the oscillator is a square wave with a rather slow rise time of approximately 20 to 30 microseconds and very sharp fall time of less than one microsecond. The falling edge of the square wave is used by the three phase square wave oscillator. The sharp fall time is differentiated by the input circuit of the oscillator and amplified to produce a negative pulse of approximately 12 136 volts magnitude and 1/Z microsecond duration to provide a reliably acting trigger pulse for the oscillator. B. Three Phase Square Wave Oscillator The three phase square wave oscillator produces the basic three phase time reference for the inverter. The output voltage of the oscillator is three square wave -¢oltages displaced exactly 120 degrees in time. The amplitude of the square wave output voltage is approximately 10 volts peak to peak and has a frequency of one-sixth of the clock frequency or 400 cps. The oscillator is constructed of three interconnected flip-flops (see schematic diagram on Figure 4-120), an input pulse shaper, and an "and" gate. The input pulse shaper circuit has a Z. 4 KC clock output for its input. The clock output voltage is differentiated and amplified by the circuit to produce a very sharp negative pulse which is used to trigger the three flip-flops. The three flip-flops are connected by the steering resistors R6, R 7, R15, RI6, RZ4 and RZ5 to form a turn "off" mode rL-_g counter. These steering resistors serve to control the counting sequence of this ring counter with the introduction of each negative trigger pulse. Assume that transistors Q3' Q_ and QA of the ring counter are put in a saturated state from apre_vious nggative trigger pulse. Examining the voltages across the base circuit steering diodes reveals that diodes D_, D_, and D have large reverse bias voltages across "- b 7 them while diodes Dy D 4, and D 6 have small reverse bias voltages across them. However, only the saturated transistor Q5 has a small reverse bias voltage across its steering diode D 4. Thus the next incoming negative trigger pulse will turn "off" transistor Q5 which in turn will cause trausistor Q& to saturate changing the state of the ring counter. The flip-flops w'dl continue to change state sequentially with each negative trigger pulse. Thus six negative trigger pulses will be required to make a complete count on the ring counter. Therefore, the output frequency of each flip-flop is one half of the frequency of the effective input pulses or 400 cps since the clock frequency is Z. 4 KC. The "and" circuit consisting of the diode-resistor-capacitor-transistor network on the right side of Figure 4-1Z0 insures that the three flip- flop sequencing network does not lock into an undesirable mode of operatio.u. The undesirable mode of operation is when all three 137 flip-flops act as one and the output voltages are in phase and at the wrong frequency. The accuracy of the phase separation of the three square waves is maintained to less than one-sixth of a degree and is a function of the stability of the 2. 4 KC clock. C. Current Reference Circuit and Attenuators The current reference portion of this circuit is shown in the lower section of Figure 4-122. The circuit consists of a current trans- former, a burden resistor, a full wave rectifier bridge, and a small filter section. The load current in the output lines produces a proportional voltage at the output of this circuit. This voltage is then compared with reference diode D24. The polarities are arranged such that the potential of Point X is always negative with respect to ground until the load current exceeds twice the rated load current. When twice the rated load current is exceeded the potential of Point X becomes positive and begins to turn on the shunt blocking transistor QI9. The shunt blocking transistor acts as a variable resistor which shunts the output current from the three phase oscillator to ground thereby reducing the voltage at the output of the emitter follower. This portion of the circuit is called the attenuator. The function of the current reference and attenuator circuit is to vary the amplitude of the modulation signal to the following stages of the inverter which will reduce the amplitude of the fundamental voltage at the inverter output terminals. The reduction of the output voltage will reduce the output current thereby stabilizing the maxi- mum load current to approximately Z00 percent of the rated load current. When the inverter is operating in this mode, it appears to be a constant current generator and when the overload is removed the inverter returns instantaneously to its correct operating mode of a constant voltage generator. D. Tuned Amplifiers The tuned amplifiers operate on the square wave reference voltages and transforms them into ultra-pure sine waves. The amplifier , consisting of transistors Q10' Qll' Q12' is used as a very sharp band pass amplifier as shown in Figure 4-124. This is accomplished by using a twin - T, R-C filter network in the feedback of this amplifier. The twin-T null frequency is adjusted to 400 cps which 138 is the fundamental frequency of the square wave that is introduced into this amplifier. At this null frequency of 400 cps, the output of the twin-T filter network is zero, thus making the amount of negative feedback zero causing the gain of the amplifier to be the same as the gain of this amplifier without any feedback. On either side of this null frequency (400 cps), the amount of negative feed- back increases sharply which causes the amplifier gain to decrease sharply. Thus, only the fundamental frequency of 400 cps will be passed by this band pass amplifier while the odd harmonics of this input square wave will be suppressed and will not appear at the amplifier output, The out-put voltage of the tuned amplifier is proportional to the input voltage which comes from the three phase square wave oscillator via the current reference and attenuator circuits. In the event of an overload the amplitude of the sine wave voltage out of the tuned amplifier decreases. The output of the amplifier is then mixed with a sawtooth carrier frequency sweep voltage in the summing networks. E. Sawtooth Sweep Wave Generator The sawtooth sweep wave generator is a circuit that produces the sweep _ave required to accomplish pulse width modulation. The circuit diagram is shown in Figure 4-1Z6. The ramp g_neration portion of the circuit is built around QZ5. This transistor is a current generator which generates a current having a value equal to the emitter voltage divided by the emitter resistor. Since the emitter voltage is held constant by the zener diode (DZ5) in the base circuit th=_ emitter current (and therefore the collector current} is held constant. The constant current flow through C36 charges the capacitor up in a linear fashion. The maximum voltage the capacitor can charge to is the supply voltage, less the collector voltage minimum, which is approximately the zener diode voltage. Once this voltage is reached the capacitor voltage stops increasing and the ramp of voltage ends. In order to produce a repetitive sawtooth voltage, the capacitor must be dis- charged; this is accomplished with a discharge transistor (QZ6) across the capacitor. The discharge transistor gets its drive signal from the Schrnitt Trigger circuit consisting of QZY, Z8 and Z9. The Schmitt Trigger produces a signal before the collector voltage of QZ5 approanhes its minimum value and in turn causes the capacitor to discharge while it is still charging linearly. In operation, this 139 circuit produces an ultralinear sawtooth sweep wave with a frequency of 10 kilocycles. The output is taken off the collector of Q25 andpassed through a Darlington emitter follower. The high input impedance of the emitter follower p_events loading of the constant current charging circuit which would affect the linearity of the sawtooth sweep wave. The sweep wave is then connected to one of the inputs of the summing networks and is common to all three phases of the inverter. F. Summing Networks The summing networks mix the sine wave output of the tuned amplifiers and the sawtooth voltage output of the sweep wave generator. The network consists basically of a difference amplifier (see Figure 4-128); one input is the sine wave and the other is the sweep wave whose out- put is the difference between the two input signals. Summing is accomplished by inverting the sense of one of the signals but is not necessary in this case because the signal which must be inverted is the sine wave. The inversion of this sine wave merely imparts a 180 degree phase shift to the output signal and, as long as all three phases are shifted equally, no defect is imparted to the system. The emitter follower input circuit seen on each difference amplifier prevents loading of the tuned amplifier circuits. G. Slicer -Amplifier The slicer-amplifier circuit is shown in Figure 4-130. This circuit is a high-gain switching amplifier that turns on when the input voltage exceeds the reference voltage established by zener diode D32. The output of this circuit is a train of pulse width modulated pulses having a spectrum as seen on Figure 4-98. The modulation index k4 is adjusted by trimming the magnitude of the modulation signal at the input of the attenuators. This can be accomplished by adjusting the value of the attenuator input resistors R59, R64, and R69 of Figure 4-122. The output pulses from this circuit are then amplified by the driver stages. 140 H. Driver Stages The driver stages are shown in Figure 4-13Z. This circuit amplifies the pulses out of the slicer-amplifier to a level sufficient to drive the power transistors of the power stages into saturation. Each driver must supply one ampere at a three volt level to each power transistor input circuit and there are thirty power transistors to be turned "on" at once by each drive stage. The total power delivered by each driver is then 90 watts. The driver transformer that must transform the power from the drive stage to *,he power transistor is quite special because each power transistor in the power stage requires a separate drive winding. This means that each transformer (one per phase) must have sixty secondaries. Also, the leakage inductance of the transformer must be quite low because excessive leakage inductance will reduce the rise-time of the drive voltages and therefore increase switching losses and produce unwanted distortion. Unfortunately, at present, it is not possible to construct a transformer like this, the largest problem being the excessive leakage reactance between the primary and the sixty secondaries. A reasonable way out of the driver transformer dilemma is to divide the transformer into fifteen small transformers having four secon- daries each and their primaries connected in parallel. By using this approach, the driver transformer can have its secondary and primary windings interleaved in a practical manner to reduce the leakage reactance to a minimum. Figure 4-13S illustrates a method by which all coils (primary and secondary) are wound at once creating a multi- filar coil with very close coupling between every wire. This techni- que can reduce the overall leakage inductance considerably. Another advantage of using the incremental approach on the drive transistor is the more equal distribution of lead lengths when assembling the inverter. This will reduce the possibility of unwanted lead inductance differences and power drops in long wires. The driver circuit itself is quite unusual by the fact that the output transistors (Q54 and Q55" for example) are not driven into saturation. The reason for this is that if these transistors are saturated, the large number of carriers in the junction region causes a large storage time. If the transistor is not saturated, the number of carriers is less and 141 I. therefore the storage time is shorter than in the saturated case. The reduction of storage time to a minimum implies that the switching time is decreased, which is a desirable feature. The clamping of the collectors of transistors Q54 and Q55 is accom- plished with diodes D33 and D34. The base drive current turns on the transistor but when the transistor begins to approach saturation, the collector voltage tries to go below the base-emitter voltage. Before this can happen the diodes (D33 and D34) become forward biased and divert the base drive current into the collector. Since the base current required to drive the collector into saturation is diverted, the transistor does not saturate. The circuits preceeding the drive transistors are merely amplifiers and phase shifting circuits to provide drive signals for the main ,qrive transistors. Voltage Regulator Sense Circuit This circuit is a simple transformer-rectifier-filter circuit (Figure 4-135) which produces a direct-current output voltage proportional to the average output voltage of all three phases of the inverter. This direct-current voltage is fed into the control winding of the mag-amp phase-shift firing circuit of the dc-dc input voltage converter. When the inverter output voltage rises or falls, the variable voltage from the sense circuit causes the input converter to reduce or increase its output voltage thereby maintaining a constant inverter output voltage. J. Output Filter The output filter is a simple LC low pass filter section. An examina- tion of the spectrum (Figure 4-98) indicates that the maximum harmonic is the twenty-fifth and the lowest significant harmonic is the twentieth. A permissible voltage drop of 5% was allowed for full load operation which helps to determine the size of the inductor. The resultant reactance at 400 cps, that allows for a 5% voltage drop at full load current, becomes . 146 ohms. The filter inductance can then be found and is equal to 58.3 microhenry at 400 cps. The size of the filter capacitor in this LG section shall be such that the largest harmonic is attenuated to less than two percent of the fundamental voltage. The largest harmonic frequency is the carrier which is approximately 51% of the fundamental. A reduction to two percent or less of the fundamental requires an approximate reduction of twenty-five to one in the amplitude of this frequency. In order to perform the reduction, an impedance ratio of twenty-five to one between the inductor and capacitor at this carrier frequency (10 KC) 142 is required. The inductive reactance at this carrier frequency of 10 KC becomes 3.65 ohms. Therefore, the capacitive reactance should be . 146 ohms. The resultant value of capacitance becomes 109.2 ufd. VII TOTAL WEIGHTS AND EFFICIENCIES A. Estimated Weight The complete inverter, less package and heat sinks, is estimated to weigh 147. 539 lbs. This weight is distributed as follows: Power Stages DC-DC Converter Output Filter s Logic $5. 239 50.3 36.0 6.0 147. 539 lbs The logic weight is composed of the following elements: Transistors and Diodes 1.9 lbs Capacitor s 1.3 Transformers 1.2 Resistors and Potentiometers 1.3 Input Filter Components .3 6.0 lbs It is estimated that three 10 lb capacitors and three 2 lb chokes will be required for the three AC filters, hence the overall weight of 36 lbs for the output filter components. B. Estimated Efficiency The overall system efficiency is estimated to be 80.4% at full load. The losses are distributed as follows: Logic 100 watts DC-DC Converter 1012 Power Stages 1218 Output Filters 105 2435 watts 10, 000Efficiency = 12, 435 = 80.4% 143 VIII The major losses, contributed by the DC-DC converter and the power stages, are detailed in Tables 4-15 and 4-16. RESULTS OF RELIABILITY STUDY FOR 400 CPS - I0 KW PULSE WIDTH MODULATION INVERTER A reliability analysis was performed on the electrical circuitry and their electrical components for the proposed 400 cps - 10 KW PWM Static Inverter. This detailed reliability analysis is given in Appendix 4-VI. The formulas, ambient temperatures, de-rating factors, and reference material described for the reliability study of the 3200 cps - i0 KW static inverter (Appendix 4-]1 of this report) were used for this reliability analysis. The results of this reliability analysis can only be used as a design guide to point out circuits and components that have marginal designs, since the electrical circuitry was created from a theoretical design with no actual stress measurements being taken on the circuit com- ponents. The basic approach to the analysis of each component in the electrical system was made from the part failure rate point of view. The reliability block diagram that is used to represent the overall circuit configuration is given in Figure 4-VI-1. Examining this block diagram reveals that no redundant circuitry was used in the low level and pre-drive stage logic (block A through I). However, the Power Output Stages (block J) can contain redundant circuitry depending on the mode of failure and the permissiable maximum current allowed. If the power transistors should fail in the shorted mode, a maximum of one transistor in each switch leg or a total of 15 transistors in each half phase can short out without degradation of the output waveform. However, a catastrophic failure resulting in the loss of one half phase will occur if both transistors in one switch leg should fail in a shorted mode. If the transistors should fail in an open mode, a maximum of nine switch legs can be lost per half phase before the output capacity of the inverter drops below 100% of its full load rating. The overall reliability figure of Merit R for this 400 cps - 10 KW PWM static inverter is then found for each of the three possible failure modes for the power output stages as follows: A. Castrophic failure of two power transistors in the same switch leg for any of the six half phases. , Twenty minute missile launch and one month continuous operation as a satellite in an earth orbit, 144 a. /%iti = .078517 b. R =. 924484 me Twenty minute missile launch and one year continuous operation as a satellite in an earth orbit. a. _iti = .696529 b. R = .498263 B. Failure in the shorted mode with a maximum of 15 transistors per half phase (one for each switch leg) for all three phases. . Twenty minute missile launch and one month continuous operation as a satellite in an earth orbit. a. _ Itl = .024997 b. R = .975313 . Twenty minute missile launch and one year continuous operation as a satellite in an earth orbit. a. _iti = ,221829 b. R z .801014 C. Failure in the open mode with a maximum of 9 switch legs removed per half phase for all three phases. 1 Twenty minute missile launch and one month continuous operation as a satellite in an earth orbit. a. _iti = .024036 b. R = .97625 . Twenty minute missile launch and one year continuous operation as a satellite in an earth orbit. a. _iti = .213399 I b. R = .808652 These overall Reliability Figures of Merit R are rather low and can be improved. Examining Figure 4-VI-1 reveals that the power switch=_s (block J}, driver stages (block I), and the input voltage regulator (block A) have the largest total failure rates (_ T}. These large failure 145 rates were caused by the large number of circuit components required, their percent operating duty cycles, and the de-rating factors assigned to each circuit component. These failure rates can be reduced by selecting components with larger de-rating factors, a re-design of the circuitry to reduce its total number of components, or using redundant circuitry. The use of redundant circuitry on all circuits with large failure rates will greatly improve the overall figure of Merit R for this inverter de sign. If overload protection such as fuses is used in each switch leg then no catastrophic failure can occur for any of these switch legs. Therefore, the reliability figures of Merit R obtained for parts B-I_ 2 and C-I, 2 will be more representative of the actual reliabilities of this inverter design. 146 APPENDIX 4-1 - Analysis of the Parallel Inverter This appendix contains an analysis of the McMurray - Bedford parallel inver- ter circuit shown in Figure 4-1-1. Analytical expressions are obtained for the voltages and currents in different parts of the circuit. The effect of load on circuit operation is indicated, as well as the action of the reactive diodes. This analysis is carried out for the circuit of Figttre of 4-I-I, using SCR's. Furthermore, since the parallel inverter has a square wave output (unlike the nearly slnusoldal output possible with the series inverter} a filter is generally necessary. Since this modifies the operation of the inverter somewhat, the analysis was performed for the inverter with a filter. The filter will be assumed ideal in the sense that it presents an infinite impedance to all har- monics of the inverter output but passes the fundamental without loss or phase shift. The generalized load impedance is: AI:I:I ideal transformer is assumed, with taps at a fraction K of each of the primary windings as shown. Again, at t - o the capacitor is uncharged and both SCR's off. When SCR 1 is turned on, the equivalent circuit becomes that of Figure 4-1-2 which can be further simplified to that of Figure 4-1-3. This transformation from Figure 4-I-2 to Figure 4-1-3 requires the assumption that the transformer of Figure 4-I-2 is ideal and thus transforms the capacitor C by the square of its turns ratio from the C of Figure 4-I-2 to the 2Zc = 4C of Figure 4-1-3. Because the filter allows only fundamental current to flow, the high frequency of the initial charging current t results in its being effec- tively decoupled from the load during this first switching interval. The equation for the current in this circuit (Figure 4-I-3 isi subject to the initial conditions =0 J =0 ) (4-I-1) For a general solution, it has been assumed that an initial voltage of V o is present on the capacitor of Figure 4-I-2 (or an initial voltage of Vo/2 on the capacitor of Figure 4-I-3}. In the specific case of the first half cycle, V o will be set equal to zero in the general solution. • _ l-E ,.e ,,.,- e(E s,.@ 147 This equation is valid only when il_0 (because the SCR can be represented by a closed switch only in the region where it is carrying forward current) which holds for o_<-t __ RTT_C During the period when SCK 1 fi_cjonducting, the capacitor 4C will be charged upbythecurrenti toa value_)(where V is thevoltageacrosstheactual capacitor Ci which is given by the equation: c --g-( ) _ .-g- _-_--__ -e -- _ • I _,d-e (4-_-3i Again, this is a general expression for _ for arbitrary values of Vo; as before, for the special case of the first half cycle, we will set V o - O. Because of the presence of the reactive diodes (D 1 and D2i the voltage across the capacitor cannot rise to more than 2E/K, since if it did, it would require that one of the diodes would be forward biased. Thus, what happens is that the current i l flows into the capacitor until the capacitor voltage equals 2E/K; the current then flows in the reactive diodes. This is shown on the waveform ,drawing of Figure 4-I-ii which shows the startup and steady state operation of this inverter with a resistive load. Substituting the known value for the current (eq 4-I-2 i into the general equation 4-I-3 for the capacitor voltage results in an explicit expression for _ : _. E - _ + J- C-',/t, d _- R g _-c Jo (4-I-4 i _ _ I ' "C _ _C _: - __ -- ,,,_,° _- -- __ /_ E --C_'-- "-_ COac,l.____..s.-,--'_----,_ "2 - E on Equatlng_--(t} with the maximum v lue f V / , namely /K; e obtains the equation _or the tlrne _E when the rnaxlrnu_ c voltage is reached: Therefore -I E ! ! E (4-I-6 i 148 Since, E TT When t reaches this value, the current in the inductor is: _ (4=I-7) (4-I-8) The currents in the circuit immediately before the capacitor C reaches its maximum voltage of 2E/K are shown in Ftgure 4-I-4. The currents imme- diately after are shown in Figure 4=I=5. The current i2 is now forced around the SCR 1 - D1 loop by the inductor L; the current i 3 flows in order to main- tain the NI relationship in the output transformer. The voltage across the fraction of the transformer between D1 and the battery is E; therefore the voltage across that part of the transformer winding between D1 and SCR l is given by E _ . Assuming the diodes and SCRIs have no internal drops, (_ this voltage is the only one opposing the change of current in L, and this current thus decreases at a rate of _ (1-KJ amp/sec. (4-I-9) L (K) The time required for the current to die to zero is thus given by _3 seconds (4=I- 10) and the current i 2 during this interval is given by: C __ -- _--==) ----P_, E _ E (4-l-It) where t - o is the time of initial gating on of SCK 1. (This is just a linear decay in _ seconds from the initial value of the current as given by equation 4-I-8.i 149 The current i3 which must flow to maintain the NI relationships in the output transformer is given by /P <4,,2i and the integral ;:.E d e = represents the excess energy stored in the inductor being returned to the battery. These currents are also shown in the waveform drawing of Figure 4-I-10. (4-I-13i From these equations can be seen the reasons for having K16i where Wo is the f_damental (output) angular frequency of the inverter (and filter) andS) z is the angle of the combined load and filter impedance as seen by the power stage. Under the assumption that the commutation time is small compared to the period of the fundamental frequency, the load current during the commutation interval is approximately constant. This value may be any- where between -A and +A depending on the phase angle of the load impedance as seen by the inverter output transformer. Furthermore, with the operating frequency much less than the natural resonant frequency of L and C (which will be on the order of 20 KCi, the voltage developed across the inductor L by the changing current at the fundamental frequency is negligible. Under these assumptions the voltages and currents during the commutation period will be examined. Imnuediately prior to the turning on of SCR 2, the voltages and currents in the circuit are as shown in Figure 4-I-6. (For this discussion, an inductive load has been assumed, so at the time of commutation of SC1% 1, there is a current flowing in it from the load. i SCI% I (about to be commutatedi is carrying i 4 the (1:1) transformed load current i L. -e - ,t, - A - A c _Io t,),. ) " 1-17i 151 At the instant after SCR 2 is turned on, the voltages and currents are as shown in Figure 4-I-7. Since the filter maLntalns the load current constant at Io at the time of switch- ing, the transformer, in order to maintain the relation _NI - 0, must carry a primary current of Io as shown. Since the current must also be maintained in the cormwutatlng choke, the current path shown for i5 is the only one possible. (Any current in the now unused haLf of the primary which would be in the proper direction to maintain the transformer NI relationship would have to flow in the reverse direction through SCI_ 2; this is not allowed, i SCR 1 will be reverse biased until the capacitor voltage reaches zero. If this were the only current flowing, the capacitor would reach zero volts at Lh T - C _ E = _ EC _4-_-lsi - I I_ However, there will also be a current flow into the capacitor as SCP_ 2 attempts to charge it up to 2E through the transformer. The current directions for this action are shown in Figure 4-I'8. An exact solution for the available turn-off-time (under the assumption that the load current does not change during the commutation interval i can be obtained as follows: Figure 4-I-9 represents the circuit as SCK 1 is turned on. Here Io is the reflected load current (assumed constant, as shown i and i is the capacitor charging current. Under the assumption that the transformer is ideal and that the load current remains constant during commutation, the equivalent circuit of Figure 4-I-9 becomes as shown in Figure 4-I-10. The equations for this circuit are Eliminating VC/2, there results E - h_--_ - .:: t 4c I: Differentiating this and rearranging terms yields: _ 4LC 4Lc (4-I-20) (4-i-21i 152 Subject to the initial conditions: _ _l-e/t=o-- L. This has the solution: =0 I 0 (4-I-22) i -- -Z I_ +El, Cos_ + The total cua-rent into the capacitor is then i + 2_or N _- (4-I-24) The voltage on the equivalent capacitor 4G will t]aen rise £rom %,o/2 (where %'o will actually be a negative namber) through 0 towardm itm final value E/K. H_wever, once the capacitor voltage p assem throlagh the zero point, the SCR being commutated (in this case SC_ 1) is again £orward biased, ending the available tlx_-o_-poriod. The charge that m_tst be added to the capacitor to accomplish t_s voltage ckange is / (4-I-2S} but 1_ J,, Z' _'- --:jC_-:t-z_;) Equating these two values o£ _q (and per£orming the integration) there results Combining the sines and cosines trigonometrically results in the equation: ?]- which has the solution: (.4-'r-ie'_) 153 For the case of a very large current to commutate, this expression reduces to (using the approximations 51 ^f_ N I_ ._= _);-['A_- _ 6:9 for _ very small and assuming that _ _ --'L:__ E) _ ii_ [ ___-CE __ --_C__o_3_ _[[oCEwhlch agrees (4-I-30j with this limiting case value obtained from other reasoning (equation (4-I-18ii. The voltage across the capacitor is then(for an initial voltage of -2Ei: C -- Clearly, the value of v c at any time t will vary as Io varies, so, as a limiting case, the situation where Io is very large will be investigated. For this case the equation for v c can be written approximately (using the small angle trigo- nometric relations _I_4 _ _- _j Cc,<5 69 _ I for 8 very small i .b'-6 -- yo/-Y._ C (4- I- 32) and 3"* the time at which .'\ -_ --_ is givenby _ - 4CE _-t--'___-r_-o (4-i-33j When t reaches this value, the load current, which previously went into the capacitor, now flows into the reactive diode. Because the capacitor was charged up so rapidly, the amount of extra current built up in the commutating inductor is negligible. The current trapped in the commutating choke (the sum of the load and capaci- tor charging currents at the instant when the capacitor voltage reached E/K, although in this case the capacitor charging current has been taken as negligible compared to the load current) then decreases at the rate of /(I- I_'/h amps/sec until it reaches zero._E For accurate results, the actual final current in the inductor should be used as the starting point of this linear decay. From equation 4-I-23 and Figure 4-I-9, it can be seen that the current in the inductor at any time t for which these equations are valid (which is the time from the start of commutation until the reactive diodes start to conduct} is given by 154 and the largest value of t for which this is valid is given by the solution of equation 4-I-26 for the case where The reactive load current continues to flow through diode D 1 however, result- ing in a back bias of E {1-I_ volts on SCR 1 through the action of the trans- K former windings. This reactive current is in a direction so as to charge the battery, indicating that, in this portion of the cycle, reactive energy stored in the load during a previous cycle is being returned to the d.c. supply. Some- time he.fore the half-cycle is hal_ over, the load current must reverse its direction, and energy once again flows from the battery to the load via current through SC_ 1 and the commutating choke. When the half cycle is over, SCI% 2 is turned on and the process repeats, but with the load current reversed and SCI% 1 and D1 changing places with SCR 2 and D2. This is shown on the wave- form drawing of Figure 4-1-12 which, like the previous one for a resistive load (Figure 4-1-113 has the first portion o£ the cycle expanded to show the commutation process in detail. From previous equations (4-I-18, 4-1-29, 4-I-30) it can be seen that for the parallel inverter there is a maximum load current that can be cornmutated; exceeding this value will result in inadequate turn-off time. For this reason, the simple parallel inverter will not operate with a short circuit or under any other condition which would result in an excessive current flow at the time of commutation. Excessive current not due to the load can occur on starting a parallel inverter if the residual flux levels in the output transformer are not considered. For example, Figure 4-I-13A shows (dashed line} a typical hysteresis loop for a toroidal core, and(solid line) a B-PI curve on which it would be desirable to operate, from the point of view of making maximum use of the core material. However, because the initial flux level in the transformer could be any_vhere between -B r and +B r where B r is the residual flux resulting from the maximum flux level at which the transformer is operated, the first half cycle of applied voltage could easily result in saturating the core. Should the resulting excessive magnetizing current exceed the maximum commutatible load current, the circuit would malfunction. Also, because toroidal transformers have a very high ratio of B r to Bnmx, and because of their high permeability tend to drift towards one end of the hysteresis loop under any slight unbalance in the drive, even in a core designed for operation at a low flux density it is possible to end up at a flux level very near to the Bma x of the core material. This is shown in 155 Figure 4-I-13B, where the dashed llne again represents the B-H characteris- tic of the material and the solid llne the desired (and expected i hysteresis loop. The dotted line indicates the loop that would be obtained in the steady state with a slight unbalance in the drive to the transformer, as could occur due to dLfferences in the voltage drops across the switching elements. If an inverter were shut off while operating in this mode, and the next time it was started, the first cycle was of such a polarity so as to further increase the magnitude of this flux, the core would be driven far into saturation and the resulting excessive magnetizing current would cause failure. Thus, unless special precautions are taken to eliminate these problems, toroldal (gaplessi transformers should not be used for SCK inverter output transformers. For further dlscus_on and one solution to this problem, the reader is referred to the literature. (As long as the transistors can handle the momentary high peak dissipation, inverters using transistors as the switching element will not be harmed by this occurance, i The SCR's themselves would not be damaged either, but would fall to be commutated, resulting in system failure. When using ordinary transformer cores, the air gap inherent in the construc- tion of these units results in a residual flux of approximately zero. If a transformer with gap is then so designed that the maximum operating flux density is less than I/2 of the saturation flux density, then the application of a full half cycle of voltage at the start will not result in saturation. However, it is not a very efficient use of the core materials to operate them at only 1/2 of their maximum flux levels. This starting problem can be overcome by making the first half cycle of only I/2 the duration as a normal half cycle. Starting under these conditions is shown in the B-H loop of Figure 4-I-13C. Figure 4-I-14 shows the relationship between the output voltage and core flux level for this starting technique. If it is assumed that B r - 0, this will result in the core being in the proper dynamic hysteresis loop from the start, and the transformer can be designed to operate near the saturation flux level of the core material. Another variation of this half cycle start idea is to use a high frequency starting technique, where the inverter is started out at least twice the normal operating frequency and the frequency gradually lowered to the operating frequency. This results in a B-H loop which "spirals" out to the steady state condition; again avoiding saturation while operating the trans- former at near maximum flux levels in steady state operation. The B-H loop for this condition is shown in Figure 4-I-13D; the relationship between the flux and output voltage for this starting mode is shown in Figure 4-I-15. During the commutation period, two parameters of the SCK being commutated are of particular importance: the turn-off-time and the dv/dt rating. The turn-off-tlme has been already discussed. The dv/dt rating is simply the maximum rate at which the anode voltage of the SCP_ can be increased without causing the device to switch into *s conducting state. This turning on of the SCR due to rapidly rising anode voltage is actually due to the displacement currents in the gate region induced by the internal anode - gate capacitance of the SCK. For the simple parallel circuit, the value of dv/dt is given 2 op. cit. 156 approximately by dv/dt - ic/C where i c is the current into the com_-nutating capacitor, and is given by At-- Io C_< _.c-+ c 5,_'_--- {4-z-3si (This is one-half the current into the equivalent capacitor of Figure 4-I-12. i The dv/dt on the commutated SCR is tlms given by --- _C _ -- _ (4-I- 36ic_,v- ,'t___, _ ° Cos _ + _ : _. a ,- c -- c VLc JLc for values of t such that the capacitor voltage is less than 2ELK. For other values of t, the values of dv/dt are less severe than this. Besides this source of dv/dt, the shock excitation of various stray circuit inductances and capaci- tances which occur at commutation may give rise to very high frequency oscillations which yield high dv/dtls. These oscillations can be effectively damped by putting a series RC stub across the SCR (anode to cathode)o This stub will only be effective for the shock induced dv/dt|s described; it will have no value in reducing the I/C component of the dv/dt; if this is too large it must be reduced by a major parameter change. (i.e. increasing C). In general, however, SCR's are available which have dv/dt ratings sufficiently high that they are not a limiting factor in the application of the SCR. An important rating of the SCI% just being turned on at this time which must be observed is its di/dt rating. When an SCR is first turned on, the current it carries is localized in a small area where it was first turned on. Thus, if the initial current allowed by the circuit is too high, the current densities in that portion of the SCR Just turned on can cause degrading or destructive local heating. Methods used to minimize this problem are: 1. To turn on as much of the SCR as possible as soon as possible. This means the use of fast rising gate signals with a peak power capability approaching that of the allowable gate dissipation. 2. To limit the anode current of the SCR during the turn on to as low a value as possible. Some circuits, for example the series inverter, have small initial currents (see equation 2c9 Appendix i-I of QR-I of the "Optimization Study of High P_wer Static Inverters and Converters") while others, like the parallel inverter, require the SCR to carry a substantial initial current (Io). In this case, the initial current is limited to a low value for the first few microseconds by putting a small saturating reactor in series with each anode lead. 157 APPENDIX 4-II - Reliability Study For The 3200 CPS-10 KW Static Inverter A reliability study was performed on the electrical circuitry for the proposed 3200 cps Static Inverter. The study was based on electrical components used in the low level logic circuitry and power stages. Packaging techniques and electrical connections were not included in this reliability study. Thus, reliability of connectors, terminal boards, wire, solder joints, standoff insulators, buss bars, fuses, circuit breakers, etc., were not considered because a tentative package configuration has not been established at this time. The basic approach to the analysis of each component fn the electrical system was made from the part failure rate point of view. A reliability block diagram for the 3200 cps inverter was established in order to describe pictorially the mission of the various circuits and their components (See Figure 4-II-li. As can be seen from this block diagram, no redundant circuits were used. Each major circuit is represented by a large block that is identified by a letter ranging from A to O. A series of sub-blocks are assigned to each major block to represent the individual circuits and/or components that are required to create a major circuit. Each sub-block is assigned an identLflcation number. The reliability block diagram may now be used in conjunction with the repre- sentative circuits for each sub-block to establish an overall Reliability Figure of IV[erlt R for the 3200 cps i0 KW Static Inverter. In order to determine this Reliability Figure of Merit R, failure rates for the various components of the sub-block circuitry must be established. The operating time for each component must also be known. When these two requirements are obtained, the Keliabfllty Figure of IV[erlt i_ may be found from the following formula: R - e - ti (4-n-li where: R " Overall l_eliabiltty Figure of Merit for the 3200 cps - i0 KW Static Inverter. _j= Failure rate of the ith component. ti = Operating time of the Ith component in hours. - Symbol for summation. e " Base for the natural logarithms. 158 INow the Failure Rate_ is derived from the following relationship: / - E C4-m2i where: / is the Generic Fa ilure rate of each component in failures per 106 hours or 106 cycles._ is the resultant Generic Failure Rate. K A = is the application or derating factor for each component. K E = is the environmental operating modes that will be encountered in the assigned mission for the 3200 cps Static inverter. • (The Generic Failure rate is a frequency function. It has a statistical connotation as it is relative to the number of failures that would be expected to occur over a large number of cycles or a long period of time. Thus two types of operations are considered as failure rate bases for this analysis. They are time dependent operations and cycled operatlons, i Two mission profiles were established for the 3200 cps Static Inverter as follows: l} 20 minute missile launch and 1 month (720 hours} continuous operation as a Satellite in an earth orbit. 2} 20 minute _missile launch and 1 year (8750 hours} continuous operation as a Satellite in an earth orbit. The maximum operating ambient temperature was established at +40°C. Temperatttre rises of loglc components such as resistors, diodes, and capacitors above this maximum ambient temperature were assumed to be negligible with the use of appropriate derating factors and heat sinking. Low level logic transistors were given a maximum junction temperature rise of 20°C above the worst ambient. The transistors (STC2501 i used as switches in power stages were given a maximum junction temperature rise of 40°C. A maximum hot spot temperature of 80°C was assigned to the pulse transform- ers and pre-drive transformers While hot spot temperatures of lOOIC and 120"C were assigned to the output filter inductors and power transformers respectively, 159 Parts application data sheets were used to assemble the various pertinent information required for each component in the electrical system. The coding established from the Reliability Block Diagram and part numbers from the various circuit schematics were used on these data sheets to identify each part and its function in relationship to the blocks and sub-blocks. Wherever possible, the type and manufacture of the various components were obtained from the JPL preferred parts list (JPL Specification No. ZPP-2061-PPL-D i. Deviations were recorded on the parts application data sheets. In order to obtain the generic failure rates_ f, de-ratlng factors KA, and environmental operating mode factors K E for the various components the followin E reliability data was used: "Reliability Engineering Data Series Failure Rates" by D. R. Earles M. F. Eddlns Avco Corporation - Research and Advanced Development Division From this data the values for K E can be established for each mission as follows: ii KE" 2i KE= 900 for Missile Equipment (In Flighti I for Satellite Equipment In An Earth Orbit Three generic failure rates (Lower Limit, Mean, Upper Limit i are given for each type of component in the Failure Rates - Life Expectancies tabulation tables provided in the above reference. The Mean generic failure rate was used since a more realistic result was felt to be obtained. These Mean generic failure rates _ i were recorded in the parts application data sheets. The de- rating factors K A were obtained from graphs provided in the above reference. Pertinent electrical information such as percent of operating power and opera- tlng temperatures were used to determine the de-ratlng factor K A for each component from the appropriate graphs. The resultant Mean failure rate _l for each component may now be found by multiplying the de-rating factor K A by the mean Generic Failure rate _ for each component in the parts application data sheets. Typical parts application data sheets for the input flip-flop that is used in the Phase Shifter circuitry are shown in Tables 4-II-1 through 4-II-3. This input flip-flop is included as part of block C-1 illustrated in the Reliability Block Diagram for the 3200 CPS - 10 KW Static Inverter (Figure 4-II-1). Its actual circuitry and parts list are shown in Figures 4-87 and 4-88. The parts application data sheets are divided into three main categories for convenience. 160 These categories are solid state components, capacitors;and resistors. The mean generic failure rate _ is first determined for each of these components. The de-rating factor _A is then found for each of these components after their operating parameters have been established. The resultant mean generic failure rate _%1 for each of the components can then be found by multiplying ^byA The operating time of each component in the electrical system is expressed on a percent duty cycle basis. Thus, a 100% duty cycle would indicate that a component would be operating at its rated output for the fu/1 mission time. Multiplying the duty cycle by the time 't' required for various parts of the mission, such as missile launch (20 minutes) or Satellite orbit. (1 month and/or 1 year) produces the exact time that the component is in use ti. So ti- t' x duty cycle (4-17-3) The product X t may then be found for each component for every phase of the assigned mission. The total _i ti product may be found for all the electri- cal components in the 3200 cps Static Inverter by summing the individual products _ t to the ith component. The overall Reliability Figure of Merit R was found from Equation (4-II-l) for each mission profile, Their results are as follows: 1) 20 minute missile launch and 1 month continuous operation as a Satellite in an earth orbit. b) R - .963506 2 i 20 minute missile launch and 1 year continuous operation as a Satellite in an earth orbit. i a)_ i ti = .329858 b) R " . 718930 Total failure rates_T were determined for each of the major circuit blocks that appear in the Reliability Block Diagram for the 3200 CPS - I0 KW Static Inverter Figure 4-11-1. In order to obtain these total failure rates, the resultant mean generic failure rate A j for each circuit component was first multiplied by its respective percent operating duty cycle in order to establish 161 a common base for all the circuit component mean generic failure rates. The establishment of this common base will then allow all these mean generic failure rates to be summed together in order to obtain a total failure rate _ T for each of the major reliability circuit blocks in Figure 4-11-1. This informa- tion was helpful in determining which circuit blocks and their sub blocks were contributing most to the reduction of the overall system reliability. Examin- ing these reliability blocks in Figure 4-11-1 reveals that the pre-drlve buffer stages (Blocks O and H, power stages (Blocks I and J) and the phase shifter circuitry (Block Ci have the largest total failure rates ( _ T). Their large failure rates were caused by the large number of circuit components required, the percent operating duty cycles, and the de-ratlng factor I_A assigned to each of the circult components. These failure rates can be reduced by selec- ting components with larger de-rating factors _ A. Thus using a 300 amp power transistor in place of the present 150 amp power transistor for Q9 and QI0 in the power stages (Blocks I and J) will reduce the power transistor mean generic failure rate by more than half. (At present the 150 amp power tran- sistor is the largest available.) A redesign of the circuitry in Blocks G, H, I, J, and C that would result in the elL_nination of a large number of their electrical components would also reduce their total failure rates. If it is found that the number of circuit com- ponents cannot be reduced significantly with a complete circuit redesign, then the use of redundant circuitry can be employed to reduce these total failure rates. To illustrate the reduction of these total failure rates with redundancy, Block O for example is made completely redundant with the use of two complete and independent pre-d_rive buffer stages for _ach power stage. Its total failure rate is reduced from/_T - 6.32 x l0 -6 to _ TR - .35 x i0 "6. The total failure rate of Block O is reduced by a factor of 18 to 1 with a completely redundant system. Thus the use of redundancy on all circuits with large failure rates will greatly improve the overall Figure of Merit i_ for this inverter design. 16Z APPENDIX 4-III Scaling - Class I A. Scaling Down In Power Level As the power level is reduced from 1 0 KW, there are many changes which occur in the inverter components and circuitry. The variations which occur can be divided into four types as listed below: 1 ) Continuous Component ChanKes Many components, namely those which must be especially designed for a given inverter (for example transformers, inductors, package and heat sinking, and possibly capacitors, because they are of special manufacture and made to match exactly the requirements of the particular unit being designed) vary their size, weight and losses continuously as the power rating of the complete unit is varied. 2) Step Component Changes Other components, which are not made specifically for a given size inverter but rather are mass produced for a larger market and are selected because their parameters meet or exceed those required by the particular application posed by a specific inverter, do not vary in a continuous fashion as the power level is decreased, but rather remain constant until the change in requirements is sufficient enough to permit the use of a lower power device, at which time a step change in the weight of the inverter would occur as lighter, lower power units are brought into play. Transistors and SCRts are excellent examples of this type of component, where (particularly at the higher power levels) the rnaxi- mm_n current ratings are not only discrete but fairly widely separated. It should be noted, however, that although the weight and size of these components change in a step fashion with inverter rating, the power dissipation still varies in a continuous fashion (except for the possi- bility of some discontinuity at places where the components are changed). 3) Fixed Components Some components in the inverter are completely independent of the power rating of the unit. This is best typified by the master oscillator which, for a given frequency stability, has the same size, weight and loss regardless of the inverter rating. Some of the lowest level sec- tions of the logic (starting circuits, count-down circuits, etc. ) would also be in this category. 163 4i Circuit Changes As the output level is considerably reduced, it might be possible to eliminate one or more stages of the drive amplifier circuits. If the desired output were very low (say 200 watts instead of 10 KW) it would probably be very desirable to use a completely different circuit. Since this downward scaling will be used only as far down as 2000 watts, (which represents a fivefold reduction in power) at which power level a 56 volt system would still require a peak collector current rating of 20 amperes, it appears that the circuit configuration proposed for the 10 KW unit would still be applicable at the 2000 watt level. Hence, all further discussions of the effects of scaling on weight, efficiency, and reliability will assume that the circuit concept used in the scaled down designs is the same as was used for the 10 KW origi- nal design. The scaling of the weight, losses, and reliability of the inverter proceeds as follows. ai M_nettc Components The scaling of the magnetic components o£ the 10 KW inverter downward will be based on the use of the Orthonol transformer and chokes as used for the middle-of-the-road design as outlined in Section VI - "Power Stage" - of this report. The weights and losses for these components for a complete 3 phase inverter are shown in Table 4-III-1. TABLE 4-III- 1 Item Weight Loss Output Transformer 7.4 lbs. 176 watts A.C. Filter Reactor O. 75 lbs. 8.1 watts Driver Transformers 1.5 lbs. 10 watts Delay Core 0.2 ibs. 10,8 watts TOTAL 9.85 lbs. 205.0 watts In Section III-B - Scaling of Transformers - of this report, it was shown that the weight of a transformer or inductor is related to its power handling capability by the equation W I k (Vii 3/4 (4-1II-l) 164 (where k is a constant of proportionality depending on the type and design of the comI0onent). It is shown in Appendix 4-IV that this result can be extended to a collection of transformers (not necess- arily having the same k values) and that the weight of the entire group (all those required in an inverter, for example) is still proportional to the 3/4 power of the overall volt-ampere rating (of the inverter). Using this result, the scaling can be applied to the total trans- former weight as given in Table 4-1II-I instead of having to scale each individual transformer and then sum the results. A graph of total magnetic component weight and loss versus inver- ter size as obtained from these scaling equations is shown in Figure 4-1H-Io These weights and losses include those of the out- put transformer, a.c. filter reactors, drive transformers and delay cores. These are the m_gnetic components whose size is determined by the inverter rating. O_her magnetic components, such as voltage and current feedback transformers and low level logic drive and pulse transformers, will not vary with inverter rating and hence are not included in the above scaling. b) Semiconduc_or Components I. Transistor Losses The total losses and weight of the output stage power transistors are shown in Figure 4-]II-2. Depending on the size of the inver- ter, either a 30A, 70.% or 150A transistor is used. In all cases, the maximum peak current (under the overload conditions) does not exceed 80% of the rated transistor collector current. The losses in the transistor can be divided into the forward losses (which are proportional to the square of the current and the collector saturation resistancei; the turn-off losses (which are proportional to the (constant) supply voltage, the fall time and the load current); the "off" losses (which are proportional to the leakage of any given transistor and hence are independent of the inverter output rating}_ and the drive losses which are directly proportional to the inverter rating. The sum of these losses as a function of the inverter power rating is shown in Figure 4-III- 2. 2. Diode Losses Figure 4-III-3 shows the losses in the reactive and base limit- ing diodes as a function of inverter size. These are essentially 165 linear, with a slight offset in the curve for the reactive diodes where the type of diode used is changed to a lighter one wlth a lower current rating in order to save weight. The steady state losses in the zener diodes are negligible; at the 4 KW level, a i0 watt diode can be substituted for the 50 watt device used in the I0 KW inverter reducing the weight from I. 0 Ibs to 0.6 Ibs. This is shown in Figure 4-III-4. Figure 4-III-4 also shows the variation of capacitor weight with the inverter power rating. Because of the nature of capacitors, their VA rating is almost linearly related to their size (for the same type unlt i. Hence, the capacitor weight versus inverter rating is a straight llne as shown in Figure 4-111-4. ci Logic (Control) Section The variation in weight and loss of the control section of the inver- ter is shown in Figure 4-III-5. The variation in weight and loss with inverter rating is due mainly to the reduction in the amount of drive required by the output stage transistors as the output power requirements are reduced. Since the major part of the drive required by the output stage transistors is provided by the feedback windings on the drive transformers, the extra power supplied by the pulse and sustaining drives merely serves to set this feedback in the right direction and hence does not contribute materially to the drive losses in the output transistors. Hence, these losses were not counted in determining the power stage losses and thus may be now considered as part of the logic losses without having been counted twice. d) Total Weight and Losses The weight and loss contributions from the different sections of the inverter can now be added to obtain the anticipated weight and loss for (the electrical components of) an entire inverter as a function of the inverter rating. These results are shown in Figure 4-III- 6. B. Scaling for D.C. Input Voltage As the nominal d.c. input voltage is changed, the inverter components most directly affected are the power output transistors. Assuming that 200 volt transistors will be available in the 150 amp sizes, and operating the transistors so that the actual current and/or voltage applied to the transistor by the circuit never exceeds 75% of the device rating, the circuit as described in Section VI-B - Transistor Configuration - of this report can be used over a nominal input range of 41 to 68 volts without 166 either the voltage or currents exceeding the limits. (A battery variation of +i0%j-20% around the nominal value is assumed, j When the nominal d.c. input is below 41 volts_ the maximum currents required of the transistor are excessive, and they must be paralleled to provide for this. Because of the very effective use that the multiple aperture transformer makes of the iron, the most efficient technique weight and loss-wise for paralleling under these conditions is the split transformer technique. Hence, at 41 volts, the transistor weight and transformer weight undergo a step change. Similarly, for nominal d.c. inputs in excess of 68 volts, the most efficient way of modifying the cir- cuit to avoid excessive transistor voltages is to go to a bridge configura- tion. This effectively cuts the transistor voltages in half and has the advantage of allowing the output transformer to be reconnected in a bridge configuration, thus allowing more efficient use of it. At still higher input voltage (above 90i the peak forward current has reduced far enough to allow the use of the next smallest size of transistor, thus allowing a slight weight saving. Figures 4-III-7 through 4-III-11 depict the effects of the variation of the nominal d. ¢. input voltage on the weights and losses of the various com- ponent groups making up the inverter. Figure 4-III-7 and 4-HI-8 represent weight-loss curves for the output power switching transistors and base limiting and reactive diodes respectively for the power output stages. The discreet changes in the curves represent a change in compo- nent type. The total low level logic loss and weight curves are shown in Figures 4-III-9 and 4-III-10 respectively. The largest loss and weight occur at low nom_.nal d.c. input voltage levels. The combined magnetic component weight and loss curves are depicted in Figure 4-III-11. Again the greatest loss and weight occurs at the lower nominal d.c. input voltage levels. Step changes in the curves represent a change in magnetic compo- nent designs. The total inverter weight and loss curves are shown in Figure 4-HI-12. These curves are obtained by combining the curves obtained in Figures 4-III-7 through 4-III-11 for the inverter component groups. 167 APPENDIX 4-IV Proof that a Group of Scaled Transformers Follows the Same Weight Versus Power Eating Equation as a Single Transformer Consider two transformers, A and B, with weights and power ratings as indicated. Weight Power Rating Equation 3/4 Transformer A W A PA WA= kA PA 3/4 Transformer B W B PB WB= kB PB Suppose both these transformers are scaled by the same ratio to new power /and / (i.e. PA _ PB c_ )levels PA PB PA PB / I Then the weights of the scaled transformers (A and B_will be: I 1 3/4 / = k 1 3/4 WA = kA (PA) WB B (PB) The combined weight of the old transformers was W A + WB. The combined weight of the new transformers is / I I 3/4 / 3/4 (p;) 3/4 WA + WB = kA (PA) + kB (PB) = WA_--) 3/4 + (p/) 3/4 3/4 W B B = (w + (e_) (p-_) 314 A WB) Therefore, in the case of two (different) transformers (or reactors) whose ratings are scaled by the same factor, the sum of the weights of the trans- formers are scaled by this same factor. By induction, this result may then be extended to include any number of transformers. 168 APPENDIX 4-V Scaling-Class II A. Harmonic Distortion The present design specification for harmonic distortion allows for a maximum total harmonic distortion of 5% with each individual harmonic not to exceed _. The effects of varying this harmonic distortion specifi- cation on the inverter components were investigated with the results that only the AC output filter components weight, size, and loss were effected. The power output transformer leakage reactance and winding resistance along with the phase load impedance are used to make up part of this AC output filter. Thus only a series inductor and series capacitor and a capacitor across the load are required. In order to minimize phase shift the series inductor and capacitor are tuned exactly to the fundamental frequency of 3200 cps. The present design was considered as a point of reference upon which scaling can he accomplished, The series filter inductor consists of the transformer leakage inductance of approximately 28.2 UH in series with a 13.7 UH external inductor. The series and shunt filter capacitors are 59. Z UFD and 3.12 UFD respectively. The llth and 13th harmonics are the predominant harmonics that must be filtered with the lower harmonics being canceled by the secondary winding turns ratio, (see section VI-C- AC Filter - of this report). The llth harmonic was used to determine the filter component values required for various degrees of allowable harmonic distortion, since it is the most predominant of the two harmonics. A relationship between the harmonic distortion before filtering to the harmonic distortion after filtering can be expressed as HD(AF) = iZLHI IZTFI xHD(BF) where HD (AF) - Harmonic distortion after filtering HD (BF) - Harmonic distortion before filtering (4-V-l) = Load impedance at the harmonic frequency in question (including the 3.12 UFD Shunt Capacitor) - Load impedance at the fundamental frequency (including the 3.12 UFD Shunt Capacitor) 169 Z : Series filter impedance at the fundamental frequency. SF ZSH - Series filter impedance at the harmonic frequency in question. The harmonic distortion before filtering HD (BF) can be found in terms of the relative phase shift angle (see Figures 4-80 and 4-81) required to maintain the proper load output voltage. The llth harmonic will have several maxima and minima over this relative phase shift region• The amplitudes and phase angles for the maxima will be used to determine the values of the filter components necessary to provide a specified harmonic distortion level. The maximum harmonic distortions and phase shift angles for the llth harmonic are: _ HD (11th) 32. 7" .095 65.5" . 108 98.2" .139 131.0" .219 Since the series filter components are tuned at the fundamental frequency of 3200 cps, then the series impedance Z_ F is composed of the transformer and filter inductor winding resistance and_transistors saturation resistance which are small compared with the minimum load impedance. So -- x HD (BF) (4-V-2) IZT I/ ,-_ZTH|may be found by 'specifying HD (BF)for various phase shift angles anc[ the desired harmonic distortion after filtering. The total series inductance (Lq:r) and capacitance (CsT) may be found for the llth harmonic using the relationships: I. CST Z. L ST where XH _IZTH -3 •544 x i0 X H = Z. 475 x I0 -_ CST + X LH 170 H is equal to the llth harmonic and X_ is the load reactance at this harmonic. The transformer and filte_nductor winding resistance is very small compared with the reactance at the llth harmonic and thus can be neglected. The actual series filter inductance can be found by subtracting off the transformer leakage reactance at this harmonic frequency. The transformer leakage inductance (LsT _-28. 2 UH) will be the limiting case since it must be tuned out at the fundamental frequency (3200 cps}. This in turn will place an upper limit on the series filter capacitor of 88 UFD. The inductor weight may be related to its inductance using the following relationship. WL,V (I/2 L S I2} 3/4 pounds (4-V-3} This relationship is true only when used to compare inductors of similar construction operating at the same copper current and core flux density levels. The total inductor loss (core and copper loss} and volurne are then proportional to the inductor weight. From these relationships the inductor weight, total loss and volume may now be found for each phase as a function of the specified harmonic distortion for various phase shift angles as illustrated in Figure (4-V-I to 4-V-3}. The series filter capaci- tor weight and volume for each phase can be scaled directly assuming that the same dielectric material and dielectric voltage strength are used. The scaled filter capacitor weight and volume as a function of the allowable harmonic distortion for various phase shift angles are illustrated in Figure (4-V-4 and 4-V-5). The filter capacitor that shunts the load was maintained at 3. 12 UFD since it offers a very low impedance to these higher harmonics. (X_,'--I. 45 __-90 ° under no load conditions}. The total 3(_ AC filter weight and loss may be determined from the curves of Figure 4-V-1 through 4-V-5. The total 3(_ AC filter weight curves are shown in Figure 4-V-6. Examining these curves reveals that the overall filter weight increases as the tolerance on the total harmonic distortion is relaxed. This is caused by the increase in series filter capacitor size required to tune out the series filter inductor at 3200 cps. The series filter inductance requirement gets smaller as this total harmonic distor- tion after filtering is allowed to increase (see Figure 4-V-1}o Figure 4-V-7 depicts the total 3(_ AC filter loss as a function of total harmonic distortion after filtering for various relative phase shift angles _. The losses will increase as the tolerance is reduced on the allowable harmonic dis- tortion since the size of the series filter inductors must be increased. Tightening the tolerance on the total harmonic distortion specification causes the series filter inductance to increase consequently reducing the capacity of the series filter capacitor in order to maintain exact tuning at 3200 cps. This will produce the following secondary effects: 171 ao A reduction in the voltage and current feedback sensing circuit filtering may be possible. b. An increase in the A.C. output filter response time. Co A tighter control on the proper secondary transformer turns ratio must be maintained to suppress the lower harmonics. de Improving the source and transformer regulation will reduce the size of the filter parameters required since a smaller relative phase shift angle __.__) between the reference and phase shifted ring counters will be required with a subsequent reduction in the initial total harmonic distortion. Opposite effects on items a, b, and c, can be realized by relaxing the tolerance on the total harmonic distortion specification. B. Phase Separation The present maximum phase displacement tolerance is Z'. The effects of varying this phase separation tolerance on the inverter components were investigated. The results indicate that variations in transistor saturation resistance, deviations in transformer leakage reactance and winding resis%_ance, de-tunlng of the A.G. output filters, and unsymetrlcal loading are the major contributors. The low level logic will provide negligible phase shift since it is composed of digital circuitry. Of the major contributors to this phase separation, de-tuning of the A. C. output filters with a full reactive load was investigated since the A.C. output filters are composed of both the load and the transformer winding resistance and leakage inductance. The transistor saturation resistance may also be factored in as part of the transformer reflected winding resistance. An equivalent circuit for each phase may be used to deter- mine this filter de-tuning as illustrated. E,N es Eo T 0 Eout Ein Z = L (4-V-4) Where Z T = ZL + ZS 172 Z_ is the total series filter impedance including the reflected transformer winding resistance and reactance and the equivalent transistor saturation re sistance. ZS = (RF + RT} + J (XL F + XLT - XCS} (4-V-5) where Rip = inductor winding resistance R T transformer winding resistance and transistor satura- tion resistance reflected to the secondary side of the transformer. XLF = inductor reactance XLT = transformer leakage reactance XCS = series filter capacitor reactance m Z L = is the load impedance including the shunt capacitor and is equalto 2.24 + 1.76J at F = 3200 cps An ideal transformer is assumed whose output voltages are exactly 120" out of phase. Thus on a per phase basis EIN will have no phase shift since the transformer parameters are reflected in ZS" The output voltage phase shift on a per phase basis was then determined with respect to the input voltage as the resultant filter resonance circuit was de-tuned at 3200 cps. A representative range of nominal series filter inductors and capacitors required to produce various degrees of harmonic distortion (see Scaling Class II - Appendix 4-V-A of this report) at a maximum regulation phase shift angleLeof 131" were used. They are: (for_ = 131") LST rain. = 28. 2 UH CST max = 88 UFD LST = 85.7 UH CST = 28.9 UFD LST = 164 UH CST = 15. i UFD LST max. = 321 UI-I CST min = 7. 7 UFD The amount of filter phase shift angle (L.c_o) was first calculated with the A.C. filter perfectly tuned in order to establish an initial phase shift caused by the transformer and filter inductor winding resistance and 173 transistor saturation resistance. The basic transfer gain for each value of overall filter inductance becomes: LST IE in I Z8. Z I.Fl-I .996 //+ .4" 85.7 UH .994 _ .5" 164 UI-I .993 /+ .55" t 3Zl U-I-I .99Z /+ .6" A variation of the equivalent series resistance in each phase will change this reference phase angle by a slight amount. Thus if the series resis- tance in phase A should be half of that of the other two phases the corres- ponding gain and phase shift angle for say the 321 UH equivalent filter inductor will become .996 /+ .4". The gain has increased from .992 to . 996 while the phase shift angle has been reduced by + . Z'. The angular relationship between phase A and phase B becomes lZ0. Z" while the angular relationship between phase A and phase C becomes 119.8". The reactive elements composing the series filter branch of one of the phases were then de-tuned to produce both positive and negative reactances whose magnitudes are determined by the percent of de-tuning desired, (see Figures 4-V-8 and 4-V-9). The filters in the other two phases were left tuned at the fundamental frequency. The gain and phase shift angle for the de-tuned filter were then determined as a function of the percent of de-tuning. The amount of relative phase shift angle/O_ caused by this de-tuning was determined by subtracting the phase an_le ___obtained as a function of de-tuning from the reference phase angle_x%obtained for this phase before the series filter elements were de-tuned. The relative phase shift angleZ_for each of the four equivalent series inductors and capacitors were then plotted as a function of the percent of filter de-tuning and are illustrated in Figures 4-V-8 and 4-V-9. The filter capacitor (3. lZ UFD) that shunts the load was not changed when the filter was de-tuned. Assuming that the filter components produce an initial amount of de-tuning as shown in Figures 4-V-8 and 4-V-9, the filter can be re-tuned to the fundamental frequency (3200 cps) by placing a suitable inductor or capacitor in shunt with the respective series filter inductor or series filter capacitor. Using the data obtained for the amount of reactive unbalance obtained at 174 the fundamental frequency as a function of the percent de-tuningjthe necessary trimming inductance or capacitance may be found to re-tune the filter. The necessary trimming components (inductor or capacitor} weight and total loss may be found as a function of the amount of corrective re-tuning required. The same weight and loss scaling techniques used for scaling the series filter elements in Scaling - Class H - Appendix 4-V section A of this report were used here. The weights and losses of these trimming inductors and capacitors can now be combined with the weights and losses for the A. C° output filter components to obtain a complete A. C° filter weight and loss for each phase. The total weights and losses for all three phase A.C. filters may now be plotted as a function of the percent output filter de-tuning that must be corrected as shown in Figures 4-V-10 through 4-V-13 for both capacitive and inductive trimming. The four curves in each of these figures represent the total 3(_ A.C. filter weight and loss as a function of percent de-tuning for four combinations of series inductance and capacitance. These four combinations represent a wide range of permtssable harmonic distortion at the phase angle L_ of 131 °. Curve 1 represents the extreme case in which only the reflected leakage inductance of the power output transformer is used as the series filter inductance. It is theoretically assumed that a shunt trimming inductor can be placed across this leakage inductance in order to establish a reference curve as shown in Figures 4-V-10 and 4-V-12. The slopes of the four curves in Figures 4-V-10 and 4-V-11 increase progressively as the equivalent series filter inductance is increased. This is to be expected since the series filter capacitor weight is reduced in order to maintain resonance at 3200 cps. The converse is true for the four curves in Figures 4-V-12 and 4-V-13 for capacitive trimming. Since the dielectric material for the A° C° filter capacitors has not been determined at this time, it is assumed that their losses are negligable compared with the inductive components. Thus the four curves in Figure 4-V-13 have no slope as a function of percent output filter de-tuning. Also the losses attributed by the output power transformer and power transistors were not included as part of the external Ao C. filter losses since they have been tabulated elsewhere. The effects of reducing the permissable relative phase shift tolerance on all of three phases below 2 ° will require the following measures: al A tighter tolerance will be required for the series filter inductors and capacitors as well as the load shunt capacitor for each of the three phases for a prescribed harmonic distortion level. 175 be A more exact tuning between the series filter components for each of the three phases will require some trimming components which will increase the weight and loss of the A.C. output filters. Co The series filter components may have to be temperature compen- sated over the required operating temperature range to insure proper matching. GQ The output power transformer design will have to be given more careful consideration in order to minimize its leakage reactance and winding resistance and to provide as close a balance between its three output phases as possible. e. Th_ power transistors and reactive diodes should be matched for forward voltage drop and saturation resistance as close as possible. The tolerance requirements on items a through e can be relaxed corres- pondingly with the relaxation of the allowable relative phase shift tolerance. C. Voltage Kegulation The present design specification for output voltage regulation allows for a tolerance of ±2% for steady state load conditions with the source voltage held constant. The effects of varying the voltage regulation tolerance on the inverter components were investigated. The results indicate that variations in transistor saturation resistance, transformer leakage reactance and winding resistance, de-tuning of the A.C. output filter, Q of the series filter inductor, and unsymmetrical loading are the major contributors. Since the transistor saturation resistance and transformer winding leakage reactance and resistance can be reflected to the secondary side of the transformer such that they combine with the series elements of the A.C. output filter, de-tuning of the A.C. output filter with a full reactive (. 7 PF) load was investigated as being the major factor in contributing to the voltage regulation problem. This was the same filter and load con- ditions that were used to specify the relative phase shift angle as a function of de-tuning in Scaling - Class II - Appendix 4-V- Section B of this report. Again an ideal transformer can be assumed whose output voltages are exact in magnitude and do not vary from no load to full load. Thus on a per phase basis E will have no magnitude change or phase shift since the transformer aIn_ transistor parameters are reflected into the filter. The magnitude of the voltage across the load (Eout) can then be determined with respect to the input voltage as the resultant filter resonance circuit 176 was de-tuned at 3200 cps for each phase. The same representative range of series filter inductors and capacitors as was used for the Phase Separa- tion investigation (see Scaling - Class H - Appendix 4-V - Section B of this report) were used again. The percent voltage regulation can be defined as follows: % regulation I00 x IE no load I -IE full loadl (4-V-6) The shunt filter capacitor (C_ = 3. 12 UFD) is the only output load in the no load case and is equal to _. 92 L-90" at F = 3200 cps. Using the no load - tuned filter case as reference the following formula may be used E (no load} out = Z L no load (4-V-7) E (no load) in -ZT no load where ZL no load = 15.92 Jt Z T = Z Lno load + filter Z filter = R + 0 Jfor a tuned circuit S S The resultant no load gain may now be found for the four representative inductors using ZS for each case. Th_ results are as follows for the tuned circuit: E out (no load} L I S E in (no load}S 28.2 UH .01919 + 0J _ 1 85.7 UH .02321 + 0J _ 1 164 UH . 0269 + 0J /Xs 1 321 UH . 03293 + 0J _ 1 So in all four cases approximately unity gain is obtained. Thus: E in (no load)evE out (no load} I 177 But E in (no load) = E in (full load) for the ideal transformer. So sub- stituting these results into the regulation equation produces the following results. % regulation,_ E out (Full load) -i x i00 L E in (4-v-s) The resultant transfer function gain data obtained from Scaling - Class II Appendix 4-V - Section B of this report for the four representative filter inductors may now be used to determine the output regulation as a function of the percent de-tunlng (see Figures 4-V-14 and 4-V-15). The no load tuned transfer function for each representative inductor was used as a reference. Since Figures 4-V-14 and 4-V-15 and Figures 4-V-10 through 4-V-13 have the same percent of de-tuning scale on their axis of abscissas, the total three phase A.C. filter weight and loss may be found as a function of percent output voltage regulation by using the appropriate curves. The effects of reducing the voltage regulation tolerance across the phase loads below mZ% will produce the following requirements. a. A more exact tuning between the series filter components for each of the three phases will require trimming capacitors and/or inductors which will increase the weight and volume of the A. C. output filters. b. A closer tolerance will be required for the series filter inductors and capacitors as well as the load shunt capacitor to insure balanced outputs for all three phases. Co The series filter components may have to be temperature com- pensated over the required operating temperature range to insure proper matching. do The output power transformer design will have to be given more careful consideration in order to minimize its leakage reactance and winding resistance with as close a balance between the three output phases as possible. e. The power transistors and reactive diodes should be matched as close as possible for forward voltage drop and saturation resistance. f. An increase in the voltage feedback gain will be required with a decrease in voltage regulation tolerance. This may require another differential amplifier stage thus adding the following additional parts: 178 go Part Number Transistors 4 Resistors 5 Unsymmetrical loading may place too large a requirement on the averaging type of voltage regulator that is presently proposed. This will require that each phase be independently voltage regulated. The resultant circuit changes for the same 10 KW inverter are as follows: . Three separate power output flux-adding transformers will be required, one for each phase with an increase in weight of Z. 3Z lb, and in total losses of 55.5 watts using the Orthonol transformer design as a reference. o The pre-drive reference phase can remain the same. However, three times the power switching transistors and pre-drive circuitry will be required for the flux adding phase shifting stages. . A substantial increase in the complexity of the low level logic will be encountered. Two additional ring counters containing six flip-flops each, two complete phase shifting networks, and two differential amplifiers will be required. This will increase the parts count as follows for the above items. From T o Transistors 80 240 Resistors Z09 627 Diodes 66 198 Capacitors 7Z Z16 Zener Diodes 24 7Z Magamps could be used in the output side of one ring counter that would go to the drive stages of each output transformer replacing the cascaded phase shifting circuitry and operational amplifiers. Three times the number of magarnps would be required for individual phase voltage control 179 compared with those that would be used for the averaging voltage control. However, the inaccuracy in the magamps gains would cause additional harmonic distortion and additional filtering problems. The tolerance requirements on items a through f can be relaxed corres- pondingly with the relaxation of the allowable output voltage regulation. An averaging type voltage regulator may be used again with a substantial reduction in electrical components compared with the three individual phase voltage regulators proposed in item g. D. D.C. Variations The present design specification for the D.C. variations caused by the internal impedance of the source allows for a D.C. variation of + 10%, -Z0% about a nominal voltage V. In the present design V = +56 volts. The averaging type voltage feedback circuit allows the phase shifted stepped waveform to swing from//(_ _- + 16" at 44. 8 V for its full load case to_ "-90" at 61.6 V for the no load case in the present design. However, provisions are made to provide a phase shift of 180" for soft starting if this feature is required. Using the present design as a reference the reduction of the required phase shift angle will consequently reduce the allowable D.C. variations on the source. Thus the following improvements can be realized_ a. Source regulation tolerance is reduced and hence its unloaded voltage must be lowered as a function of phase shift angle O. Max. Source Max. No Load Max. Phase Shift Angle Regulation Voltage _._ 37. 5% 61.6 90" lZ. 4% 49 60" 1.6% 44. 3 30" b. Assuming that the same window area and wire size are used for both primary and secondary windings of this output transformer, the weight and weight-loss product will be reduced for these lower source regula- tion tolerances as follows: 180 Percent Weight Weight Loss Product Max. Phase Shift Reduction Lb. - watts Angle L_ 0% 1300 90" 14. 5% Iii0 60" 18.8% " 1055 30" c. If no soft starting is used then the required number of phase shifting stages can be reduced. Each phase shift stage will provide exactly 30" of phase shift. So the total number of parts that can be saved compared with the present six stages of cascaded phase shift are: Min. No. of Required Total No. of Max. Phase Shift Stages Parts Saved Angle ___9 3 153 90" 2 Z04 60" 1 255 30" d. Reliability can be improved for the phase shifting circuits with the reduction of the number of stages as follows: Required No. of Stag es Overall Reliability No. R For the Phase Shifting Max. Phase Shift Angle L_ Cir c uit s Month Year 6 .995178 .957967 180" 3 .997358 .976765 90" 2 .998087 .983144 60" 1 .998814 .989511 30" e. The switching losses in the input voltage regulator for the low level logic will be reduced with the reduction of the no-load source voltage: 181 Reduction in Input Regulator Switching Los ses Maximum Phase Shift Angle 0% 90" 12.8% 60" 17.3% 30" If the tolerance on the source regulation is allowed to increase, then the limit for this particular transformer design will be determined by the maximum flux density that the output transformer can support and the limit on the switching translstor_s collector to emitter voltage ratings before a bridge configuration is required. (At present a 150 VP - 150A power transistor is available for switching. ) The absolute voltage limit appears to be about 70V no load across these switching transistors for the present design. At this voltage, the safety margin for the power transistor is zero since the actual voltage seen across this transistor will be 150 VP. (Obtained by adding 2 x 70 VP + 10V, where 10V is obtained from the timing core. ) This increase in the input voltage tolerance to 70 VP will require the voltage feedback in the present design to operate in the phase shift region between 90" and 120". This increase in phase shift angle and upper voltage tolerance will have the following effects: a. Source regulation tolerance is increased and hence its unloaded voltage must also be increased as a function of phase shift angle //_. B/lax. Source Regulation Max. No Load Voltage Max. Phase Shift Angle _) 37.5% 61.1 9O" 58.4% 70 105" bl Again assuming that the same window area and wire size are used for both primary and secondary windings of this output transformer, the weight and weight-loss product will be increased for this larger source regulation tolerance. Percent Weight Increase Weight Loss Product Lb - watt Max. Phase Shift Angle ___O 0% 1300 90" + 9.2% 1420 105" 182 CQ d. e. The minimum number of phase shifting stages will be increased. Min. No. of Req, Stages Total No. of Parts Max. Phase Shift Saved Angle ___ 3 153 90* 4 102 105" Rel/abillty can be improved for the phase shifting circuits with the reduction of the number of stages Req. No. of Stages Overall Reliability No. R For the Phase Shifting Circuits Max. Phase Shift Angle ___ Month Year 6 .995178 .957967 180" 4 .996630 .970454 I05 t 3 .997358 .976765 90 e The switching losses in the input voltage regulator for the low level logic will be increased with the increase in the no-load source voltage. Increase in Input Regulator Switching Losses Maximum Phase Shift Angle Le O_ 90" 8.69% 105" 183 APPENDIX 4- VI Reliability Study For The 400 cps - 10KW P. W.M. Static Inverter A reliability study was performed on the electrical circuitry for the proposed 400 cps - 10KW P. W.M. Static Inverter. The formulas, ambient temperatures and reference material described for the reliability study of the 3200 cps - l0 KW Static Inverter (Appendix 4-11 of this report) were used again. This relia- bility study only included the electrical components that were used in the low level logic circuitry, input voltage regulator and power stages. Components such as terminal boards, connectors, wire, standoff insulators, etc., were not included since a tentative package configuration has not been established at this time. Again, the basic approach to the analysis of each component in the electrical system was made from the part failure rate point of view. Parts application data sheets were used to assemble the various pertinent information required for each component in the electrical system. Typical parts application data sheets for the Sawtooth Sweep Generator (Block F of the Reliability Block Diagram for the 400 CPS - 10KW P. W.M. Static Inverter), are shown in Tables 4-VI-1 through 4-VI-3. Its actual circuitry and parts list are shown in Figures 4-126 and 4-127. The parts application data sheets are catagorized as to the general type of electrical component such as resistors, capacitors, and solid- state components. The mean generic failure rate _ is first determined for each of these components. The de-rating factor _A is then found for each of these components after their operating parameters have been established. The re- sultant mean generic failure rate _/ for each of the components can then be found by multiplying _A by _ . A reliability block diagram for the 400 cps P. W.M. inverter was established in order to describe pictorially the mission of the various circuits and their components (see Figure 4-VI-I). Examining this block diagram reveals that no redundant circuitry was used in the low level and pre-drive stage logic (Block A through I). However, the Power Out- put Stages (Block J) can contain redundant circuitry depending on the mode of failure and the permissible maximum current allowed. In the present system, the Power Output Stages (Block J) contain fifteen (15) transistor switch legs in parallel for each half phase (see power stage schematic - Figure 4-i09). Each of these switch legs contains two transistors in series thus requiring 30 power transistors per half phase and a total of 180 power transistors for all three phases. Power transistors usually fail fnthe shorted mode of operation. Thus, a max- imum of one transistor in each switch leg or a total of fifteen transistors in each half phase may short out without degradation of the output waveforms. However, if both transistors in one switch leg should fail in a shorted mode, 184 then the loss of a half phase will occur resulting in a catastrophic failure of the inverter. Fifteen switch legs are required for each half phase to provide sufficient capa- city for a sustained Z50% overload. Should some of these switch legs be lost through the failure of the power transistors in the open mode, then a minimum of six switch legs will be required for each half phase to provide 100% load capacity. Thus, three possible failure modes have been presented with the failure of two transistors in the shorted mode in the same switch leg producing a catastrophic failure in the inverter. The overall reliability Figure of Merit 1t was found for this 400 cps - 10KW P. W.M. Static Inverter for each of the three possible failures modes for the power output stages using equation 4-II-1 of Appendix II and the data recorded in the parts application data sheets. The equivalent failure rate_ewas deter- mined for the redundant segments of the output power stages using the follow- ing equation: o < <.Iwhe re where _ N t = equivalent failure rate of N redundant circuits = number of redundant circuits = resultant failure rate of each switch leg = time in hours of switch leg operation Thus, N 1 = 1 was used for the catastrophic failure of two transistors shorted in the same switch leg while N z = Z and N 3 = 2. 5 were used for the failure of fifteen transistors in the shorted mode per half phase and for the removal of nine switch legs due to open transistors per half phase. The three reverse current blocking diodes that are used to supply the DC power to the fifteen parallel switch legs for each half phase may be considered as partly redundant since the loss of one due to an open Junction will permit a maximum of ten switch legs to continue to function. A loss of two diodes in the open mode however, will only allow five switch legs to operate which will limit the capacity of the inverter below the 10KW design level. N 4 = 1.5 was then used for the loss of one reverse current blocking diode that had failed in the open mode. The overall reliability figure of merit R for this 400 cps - 10KW P.W.M. Static Inverter was then determined for each of the three possible failure modes for the power output stages as follows: 185 A. m. Co Catastrophic failure of two power transistors in the same swltch leg for any of the six half phases. i) 20 minute missile launch and 1 month continuous opera- tion as a satellite in an earth orbit. a) _ iti = .078517 b) K = .9 24484 2) 20 minute missile launch and 1 year continuous operation as a satellite in an earth orbit. a) _i ti= .696529 b) i_ = .498263 Failure in the shorted mode with a maximum of 15 transistors per half phase (one for each switch leg) for all three phases. 1) 20 minute missile launch and 1 month continuous operation as a satellite in an earth orbit, a) _ i ti = .024997 b) 1% = .975313 z) 20 minute missile launch and i year continuous operation as a satellite in an earth orbit, a) _ i ti = .221829 b) 1% = .801014 Failure in the open mode with a maximum of 9 switch legs re- moved per half phase for all three phases. 1) 20 minute missile launch and 1 month continuous opera- tion as a satellite in an earth orbit. a) _ iti= .024036 b) 1% = .97625 z) 20 minute missile launch and 1 year continuous operation as a satellite in an earth orbit. a) _ i ti = .213389 b) R = .808652 186 Total failure rates _ T were determined for each of the major circuit blocks that appear in the Reliability Block Diagram for the 400 cps - 10 KW PWM Static Inverter - Figure 4-VI-1, Examining these reliability blocks in Figure 4-VI-1 reveals that the power switches (Block J), driver stages {Block I)_and the input voltage regulator {Block A) have the largest total failure rates {A T). These large failure rates were caused by the large number of circuit compo- nents required, their percent operating duty cycles, and the de-rating factor K assigned to each of the circuit components. These failure rates can beA reduced by selecting components with larger de-rating factors KA or reducing their percent operating duty cycles. A redesign of the circuitry in Blocks A, I and J would also reduce their total failure rates if a major portion of their electrical components could be elimi- nated. If it is found that the number of circuit components cannot be signifi- cantly reduced with a complete circuit redesign, then the use of redundant circuitry can be employed to reduce these total failure rates. Block J can be used as an example to illustrate this {see Figure 4-VI-I_. When no overload protection is prov_ided for each of the 90 traJasistor switch legs, a minimum total f_tlure rate _ T of 55. Z x 10 -6 is obtained. However, the total failure rate A T is reduced to Z. 74 x 10 -6 when suitable overload protection such as fuses are placed in each of these 90 transistor switch legs, thus preventing a catastrophic failure from occurring when both transistors in any one of the switch legs should fail in the shorted mode. Thus, the use of overload pro- tection in the switch legs allows more confidence to be placed in the reliability figures of merit obtained for the two mission profiles in parts B-I, Z and C-I, 2. A further reduction in total failure rates _ T for the rest of the cir- cuitry and hence, an improvement in the overall Figure of Merit R for this inverter design can be obtained with the use of redundant circuitry. 187 00 0 o o o o o 4_ r,,,l o eo °P,i 4,_ o 0 188 _o_ ._ _ o • "=_._ :_ ,_._ _ o o 0 0 o • o • o_._ o I--.4 0 H 0 E_ [fl ;> Z; H 0 0 < 0 0 ! _0 •.-.4 q u_ m 0 XU_ ®0 m "of m o • L_ d gO L_ U _ o U ° _ _ _ u_ 0 g u_ 0 u_ u_ 0 _ m 4.0 0 u o o _f _ ,._1,'_ _ e,q _o_._ _1_ ,..] _o @ o _ _e | R 2; > 0 0 0 0 0 L) _, uf ,.-1 0 2; 189 _® O g_ _C_ m ,_ O O I" o H_J r4 o x u o u-1 i_. _c_ O r_ u_ utl eq _' O O x 'd' xO N N O CO _ N O C_ • • • u'_ oh O N N .; ® O _ oo _n o _ o x _ N xo xo ,-_ N O x • R_ _ " e,_ N o3 _ N exl ,-_ r_ N C_ O .,._ ,_O _ O O U _O H t_ 0 0 N _.1 0 - m _- o o ,_ 8 N _ N 0 N -_ -0 0 Z 0 ,..1 _ 0 0 I H 190 r_ r_ o p. r_ 0 .< 191 _r,-. k_ I 192 uU,< 1 6_ * i _, ,q, J F, M 0 a M Z u_ r, o z_ _5_1 _ . g • ° _D _ o o o o U o o o • _- _ z z o • • . • • • 0i o [-i t ! o_ , < -_ < o_ < I ,..,4 o _ 6_ o o o 0 0 0 0 • • • ° ° . ), _ _ _ o o 0 0 eq e_ 0 H H H H H 1--1 ° _ 0 0 0 O 0 0 0 0 _1 _ _ _ _" _" _" _" o- I| l,i "" o_ l:l,, U I1, u l_lr'_il,., -,,..,.iXD_ _> -,. .-. m m _.i,1 = : o _ 0 0 0 _..-, &_ <_ <_ &<.., o'., f Jm U I I < ® Z u u < < "'° _ i! o_ _| •e en in en _ • . . _ _ o° 0 il!" _ _ _o _ _ _o _ _ _g ,_ _ ,.4 ,_ _ N • ...... ° ° ° ° ° ° _._ _ o _ _z _0 0 N N N N H H o _ L) .< u _ i r=l c) < = _ m _. Eo L_ & .-1 .< ['4 ..lO It_ f_r4 II.Id 0 C=I o ,o L.) o_ )- o o 41 c_ o uo J_ r_ r-- o° _> U oo o_ ._ o o_ o_ ____o o o o o _e o o • , olo ,_,_.. "f-I P_,_,_,-,: ..,_,,,,,,_< 199 V200 ro 1 _F '_z _ow LO E_L.,o l l I l l 1 _e_ I, _ I I I I I i I I , I L_ I (_u_se- 8Va_ar _Jlwr 202 V_ D :E T _ERtES L_.rN_A_ _c6u_m"roR "t" VO F,6. _-Co .+. V,H f "t" D i Vo c_ 303 -+/ \ , +,_!_+r-].nrt+ P., _i "t-<7 _,, 4-8 204 v,:.,, r- • 7 Ill OJ I ,, • lr ¢, v I ..... v I K 4" b b t _O.G -t" /j i Sr_o'-UP Cs_,r .,_T D f--I , _//ou'f J 206 + 0 r f _ Z--_ Z--- I _t 0_ 0 .J I ! _J _ v/.1 oA t F m _U t © ! _J 207 II I I 1 I I I I 1 _ 1 1 Im 1 1 1 EL z ] 1 1 r I , ! 1 1 I 1 1 i l I 1 1 _, .... ! Z08 s, [,_;; s, [,_ q r-q rq 1-1 I-q Fq F-1 r-] I-- [_1 ,,--,- _] LLL FF L !- I, F- 209 Ar X s, Y ,, r-" .,u_, I_ '_'_I ',k,__ _ 4_ s,_ ! F__,"q-18 Ez:_ I _ f t v ZlO I ! o Q Fo_ ,d-C. u.s_¢" _.11 /1 I l J I ii ; I m I i I i i ! = i \ n m / / /-i//,c:,,,t /_ c 4p, ii i 212 -->-- F'_c_,_ I2.13 ._AIV__ TE_ _; T'c N,AI & ]_OFI P L 214 TWO STEP - EQUAL TIME PHASE VOLTAGE +V Figure 4-26 0 -V TIZ TI ;p__ +'- rl Average Value of Wave£orm = 1. 0V RMS Value of W&veform = 1. 0V 4%" Tots/Harmonic Distill[on m 4B. 343 Harmonic Number 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 Percent of Fundamental PI. N. P. of F. 100. 0 33. 3 Z0. 0 14. 28 11. 11 9.09 7.69 6. 67 5. 88 5.26 4. 76 4. 35 4. 00 3. 70 3.45 3. 23 3. 03 2. 86 2. 70 2. 56 41 2. 44 43 2. 33 45 2. 22 47 7.. 13 49 2. 04 51 1.96 (ZN-I) 1 (ZN-I) x 100 215 W&ve£orm P FOUR STEP - EQUAL TIME PHASE VOLTAGE +V Figure 4-Z7 -V __T/4 --_ [ _---T/4 _ T/4--_ T Average Value of Wavefozrn -_2V R_MS Value of Wavefonn = (I/V 2)V = 0. 707V R_k_S Value of Fundamental = (Z/77" )V = 0. 636V Total Harmonic Distortion = 48. 343% Wavefoz_ Z P 216 +V 0 -V FOUR. STEP - UNEQUAL TIME TYPE A |0_I20Z.__ I r PHASE VOLTAGE Figure 4-2 8 Average Value of Waveform =r_2 3)V RMS V_ue of Waveform = ( >Z/_),y = 0. S*6_V RMS Value of Fundamental = (Z _ 3) V = 0.5513V Total Harmonic Content = 31.09_ Lowest harmonic is the fifth and all multiples of the third harmonic are zero. 217 Waveform 3 P +V oJ L FOUR STEP-UNEQUAL TIME TYPE B 46.4" T P PHASE VOLTAGE Figure 4-29 _-- 23.2 ° Average Value of Waveform = 0. 7422V RMS Value of Waveform = 0.8615V KMS Value of Fundamental = 0. 8276V Total Harmonic Distortion = Z9. 1% Dwell angle selected for minimum total harmonic distortion. Waveform 4 P 218 SIX STEP-EQUAL TIME-EQUAL HEIGHT 4 V 0 --t1.20" 80" 240 ° 300 ° ZT/ _ 360" PHASE VOLTAGE Figure 4-30 Average Value of the Waveforrn = (4/3)V = I. 333V RMS Value of the Waveforrn = _/Z--V = l.414V RMS Value of the Fundamental = (3_ I. 350V Total Harmonic Distortion = 3i. I_ Waveforrn 5 P 219 SIX STEP-UNEQUAL TIME -UNEQUAL HEIGHT TYPE A PHASE VOLTAGE vVY +-- V k q-4-_ 45" _-- 2 L135" 80 ° _225" '315 ° I- zTT 2 Figure 4-31 360 ° Average Value of the Waveform = 1. 707V RMS Value of Waveform = 1. 8477V RMS Value of the Fundamental = I.801V Total Harmonic Distortion = ZZ. 9% 220 Waveform 6 P EIGHT STEP-EQUAL TIIVlE-UNEQUAL HEIGHT TYPE A O. 414V [___ l L L I Z_ PHASE VOLTAGE Figure 4-3 2 Average Value of the Waveforrn = 0. 8536V RMS Value of the Waveform = 1.0V RMS Value of the Fundamental = 0. 9743V Total Harmonic Distortion = 23. 1_ Waveform 7 P 221 EIGHT ST EP-UNEQUA L TIME-EQUA L HEIGHT PHASE VOLTAGE Figure 4-33 _v_ 2vt I 180" Average Value of Waveform = 1. 333V RMS Value of the Waveform = 1. 5055V RMS Value of the Fundamental = 1. 483V Total Harmonic Distortion = 17.4% Waveform 8 P 222 EIGHT STEP-UNEQUAL TIME-UNEQUAL HEIGHT TYPE A PHASE VOLTAGE t 0.618V [9 "112° 180 ° -{, r I Figure 4-34 Average Va/ue of the Waveform = I. 0472V R]_4S Value of the Waveform = I. 203V RIMS Value of the Fundamental = I. 1835V Total Harmonic Distortion = 18. 3_ Waveform 9 P 223 EIGHT STEP-UNEQUAL TIME-UNEQUAL HEIGHT TYPE B PHASE VOLTAGE 0,_9083V __o_v__ , I 13.5" 4Z. 7" _ 1480" 137.3" 166. L 1 Figure 4-35 Average Value of the Waveform = 1.32 5V 1%MS Value of the Waveform : 1. 496V R/VIS Value of the Fundamental = i.476V Total Harmonic Distortion --16.6% Waveform i0 P 224 TEN STEP-UNEQUAL TIME-UNEQUAL HEIGHT TYPE A PHASE VOLTAGE Figure 4-3 6 I v (z+A_v v 3 ! zr_ I "- 3 m m" Average Value of the Waveform = (4+ 2 _ = 2. 488V 3 RMS Value of the Waveform = 2, 7329.5_V RMS Value of the Fundamental = 6"%"2_'= Z. 701V Total Harmonic Distortion = 15. Z% Waveform 11 P 225 TWELVE STEP-EQUAL TIME-UNEQUAL HEIGHT PHASE VOLTAGE . 268V_ 75" 180" _ 2V Figure 4-3 7 Average Value of the Waveform = 1. 244V KMS Value of the Waveform = 1.414V RMS Value of the Fundamental = I.398V Total Harmonic Distortion = 15.3% Waveforrn 12 P ZZ6 \9. 5* lq. 7* __ TWELVE STEP-UNEQUAL TIME-UNEQUAL HEIGHT TYPE A PHASE VOLTAGE -> _,2 G --51.9_ O. 85 IV O. 955V 1. 955V lq. 7 ° _ 9.5" 180" T t 2. 806V V / Figure 4-38 Average Value of the Waveform = I. 889V RMS Value of the Waveform = Z.125V RMS Value of the Fundamental = 2. 111V Total Harmonic Distortion = 11.5% Waveform 13 P Z27 SIXTEEN STEP-UNEQUAL TIME-UNEQUAL HEIGHT PHASE VOLTAGE Figure 4-3 9 F F V- Average Value of the Waveform = 1. 8426V RMS Value of the Waveform = 2, 0674V RMS Value of the Fundamental = Z. 0553V Total Harmonic Distortion = 10% Waveform 14 P 228 EIGHTEEN STEP-EQUAL TII%4E-UNEQUAL HEIGHT m m ]] _-II ._6o.-'1| 80" 100" ,___ 120"_____ = 140 ° = 160 ° = 180* T- PHASE VOLTAGE _--O. 347ZV Figure 4-40 ' II. O00V t l 5.4002V I.5ZO8V J - IT!o4. 0ZV I.8794VI l [jJ -l_ F k_V- Average Value of the Waveform = 3.679V RMS Value of the Waveform = 4. 064V REfS Value of the Fundaments/= 4. 036V Total Harmonic Distortion = 10% Waveform 15 P 229 ',.o ,( I I I J_ m I ....... I_ C' ,..3' o flO 18o _ -7 o Fo, " E_Ar'7 i,.._.F_ 4 -_ FaGv_E _--41 230 0 0 0 0 0 r_ 1.06 1.05 1.04 I. 03, 1.02 1.01 I.O .0 1=2 Figure 4 - 42 Ratio of Lossel i_ T_crrmL-r_ _ _,ith Equal Copper & Core Loss t_ Tza_a_orn_ers Designed with Core Loss=_la Cdpper Loss (where "&" is the exponentlln _e core loss vs. flux density re_tionship) p=C I Ba= CoreLoss U nit _roiurne i i r Z ! " .!'7" , !i_. ,''i " ___ ]. , - i',i i | , i i , i1,4 1.6 1_8 2_0 2 2 2_4 i ..... / / Z. 6 Z.8 3.0 231 1_X 2 i I l i II Figure 4 - 43 Conventional Single Phase EI "Scrapless Lamination" E .i ......... , r ml J i I I I I I X Figure 4- 44 Three Phase Lamination which uses same coils as Figure 4 - 69 / -'/ -. J Figure 4 - 45 Circular Three Phase Lamination Z3Z E Q JF! t 4I L_ J ! .....i I L---- I | • i I ...4 ] "-1 | | t--- 233 .a t_ > ¢ 1" 0_. F L..i-- /q'w,_"r'¢-_ rl,_P C D ( C o_,,.srp .x _,x Sq,v,,_r_,*.,,-,.) Z34 •t_kW-LkW-L_ • ak. I I o.J_6 1. o /, o o.aj6 NJL F ,G . "_- 4" ct _v_wT _ cui'_ _ _ • • • ' • • Z35 Z ,_ ---P ,-/ ± T 1 ¢ T "7-t-/ I C._'_ ESJ, - = ,'_ T 4- 34 .¢ T 236 !@ _u _N_OAV _I_AD N_H ,__ Q Q e e 0 O0 0 0 oo _) o_ 0 _D 0 0 237 ) ) ) _J ¢ ===-- i I I _ * ¢_z+_a I I I I I ' _) I I ) II I ) , I I I ! ,, _ I I .:! \ r _ "\ It_ '\ J / J' .f \ i I i f / l ! _-ir._RE 4"-,5"I- Z38 _IA eaA _'3A 4E a r_/A A ! : !"-- 11' J has-diS ¢3e--#_e_ II I _/_ - l _'38 3_ - _L _-,_,_ "_ - 5"5" 239 f-- _ s Jt" -I__ _.,÷,.,+ 2__ _. _(_ ± T .._/g _k ,_/_ T 3,'x 1_ ,'_ / _, T 34c ± /_/ _ -f- _2 .T ,:.'t" ± 240 I, :k 'i 7_ ,_r_" pt_._,_t,,_,_ " _,,,eC Z4_ JJ i -- Ill i i I I I ;i I II 243 T ¢ I00 v 5 0 10 ORTHONOL 0. I I0 100 Power Output (Watts) Transformer Designs 1000 Figure 4 - 61 I0,000 244 I00 ._ I0 / / 1 / / . ./ ./ / / • ! /. ! / / / ,'/.'"_-- / i/ ° . • " r/ i " • - . •+ . .. / / ,,-.,- / t,/.- 2 345 / i i / , >" f I ,' _ - <>_;, i ,' <>. ,,_.,,/ i / - t / 7'," _. / t /t . ../ f7/ # / "r/ /*/ "i 1 o . / d- .- / 2 fo r" t / f_ . J , ." /f " 7'" ' o t" ,/ SQUARE pERMALLOY 80 0. i I0 100 Power Output (Watts) Transformer Designs 1000 Figure 4 - 6Z I0,000 245 100 v Cn ._ 10 13 11" f - /11 ,, / .1-"" #( "/" .B / #;'y •-///_ ,/// -./ >/ •-3/ 12 13 SUPERMENDU R 0.1 I0 100 Power Output (Watts) Transformer Designs 246 I000 Figure 4 - 63 I0,000 Wu cD o o 00N_ o b(} o W o f o (x) o I G, 0 m _ _i O_ / I ! / r_ t,- U'3 C10 o .,D ! tf_ O t_ 0 u_ C3 0 247 t-T-P_n lv.vFo,q _ Eq _/'rH MA_ Nk'T/¢ ..qllO,_IT i i i i 248 0 O ,n {3 Q) F( p_ k • : . • / / / 249 _ ,e • . oT_w_i o ._jsu_.z.T.o / ! 0 c_ A b_ *r.4 0 v n_ 0 0 _ N i _f I I I _tG u_" E "_ "$8 25O j i| iiiii V ,/ V v V v 251 _b I ,b _ _J f,,. 1 o_ 252 I ! i __ .... j __ i ++ !+ .+ • + t • i i + +_ . + I I 253 L_ m am, /r / / I mt m _ _ z_ _ _m 1 I I ! I I ) // x) 254 ! I I t I ! I ! t I i 0 I I'- t__ ! _ ,T _F _ r-L T-I t- I I I T 'It i I ' 1] t- I I I A LA Oikf_Di_lO.4fU tDI /,IV'CHES, _ Tf,,,,/- [ I._7._" ),<_75 /.,t?S )._?S o._ 'F Fl _ o_E '#-'77 Z56 N I "_ N! ,4/'4/oo, _ - /oo AND T:_ TI >- I Ty l='l (._ l.. Z57 pre_ )1 I [ t[ FJ_u_E ?-58 ......... i .......... r ........ ; - _ i_ :,I_! t i 1: i / . _ _ i ! --t-.,,'_-,. _ i i i • i i ,, i x • t i , : __ _-____ ....... __.__ ...... ! ........... E ! _ i i ' ' ' __/itl7t: t .. , . 1 . " - | " I " "t • I 1 • • . , ! I r t 1 7 t ; ! : i l i l ] i . 1 ' ! 1 I ''_ I I I i ! 1 : ....i ; .... A i ; 1 ,: i i....... , .............. = / /!...... -r _ . : _ ! I ' t l : i'_ . : ......!.......... i .....+ ,i ._ Ill i : t : / : ; 1 : . •_ I ,.l_ I '. : i / I I i I : , r,il_ 1_.4 I I !!, ,, 1 .1 ..... _----t.........1--4-- t-- _--- 1: ®_! , i i / , t: i _i -_-:---i---_ 1 i 17 ;_ _i 1 :- 1 _--1....;....1-'-- --_-- ,-_ _i / I / : I t *' "" IlL*i. +.... _ ....... ' '+ ' I ..i ........ _..... +,.... t i "I ' "| _ _ _ " --7..... 7 i.._._.. ' " / : 1 : " i i ' | . . I _ i , • i I o o ! t. v A _.) 259 /tb I ,_._ L 261 G4"-i "4"-I -I-| -_I 4-I _6Z l3 _o/ : ¢e /4 7"_"_,,f/N4 £ _'/ _ ug£ 4- 8'¢ 263 PARTS LIST FOR TYPICAL FLIP-FLOP FOR BOTH RING COUNTERS (SlX REQUIRED FOR EACH COUNTER) Part R1 R2 R3, R4 R5, R6 R7, R8 Rg, RI0 RII DI, D2, D3. D4 DZI QI, Q2 CI C2, C3 C4, C5 Value Tolerance 3.3K - 1/2 watt - composition e5% 120K - 1/2 watt - composition _5% 22K - I/2 watt - composition e5% 15K - I watt - composition 4-5% 2. 2K - 1 watt - composition i5% 22K - I watt - composition _5_/0 270/t- I0 watt - wire wound 4-1% IN 458A IN 1518 - 3.9 V DC el0% 2N 657A 0.22q F.400 WVDC ±10% 0.001_- 300 WVDC _10% 0.001_/_- 300 WVDC 4-10% 't - 8 5" 264 _i'_'_:_ _ _I ¸ L_ I I L t t I I I t I i I I I I I i I i --I I Oc_ t Lu PARTS LIST FOR PHASE SHIFTING CIRCUIT Part No. Value Tolerance R1 R2 - R3 R4 - R5 R6 R7 R8 R9 R10 Rll R12 - R14 R13 - R15 R16 - R17 R18 - R19 R20 - R21 R22 - R23 1K- 1W Composition 1 OK - 1/2 W metal film 8.2K - l/2W Composition IK - 1/2W metal film 2.7K - 1/2W metal film 15K - 1/2W 4. 7K - 1W 8.2K- 1/2W 390_.- I/2W 22K - 1/2W 4.7K - 1W 2.2K- IW 15K- lW 22K - 1/2W 22K - 1W Co mp o s it ion Co topos ition Co topos ition metal film Co rnp os ition Comp os ition Co raps s irish Composition Composition Comps s ition .,-5,,/o .1% -,.1% ±5% +5% C1 - C2 C3 C6- C7 C4 - C5 x 000 ,e_fd - 300 WVDC 20 _afd - 300 WVDC 200 _..fd - 300 WVDC 1 00 _.t'd - 300 WVDC -,-l% il 0% -_1o% • 10% D1 - D6 IN916 D7 - D8 1N458A DZ1 1N752A - 5"._V DZ2 - DZ3 IN756A - 8- E _' DZ4 - DZ5 IN756A - 8.E %' *5% *5% ±5% Q1 - 02 2N1132 Mat ched Q3 - QI0 2N697 Input flip flop represented by block has the same comp(:ments as output flip flop except the following: C6 - C7 100 _nfd- 200 WVDC el0% C4 - C5 50/a_fd - 200 WVDC i10% FIGURE 4- 8_ 267 OO TPtJT PtlL,SE .SHtlP/tY_ C/,_C I.,,/T _ PH_ S£ ,..,cH/rTE.O COUNTLe/_ ' f"_OIY/ LA,.CT PHtT,f'E ,SH/r'r/N_ f-I-IP-F'LoP +2SV o.(.,) dl DI % 4 :8 -[6.Z'_vp uT OF PHA._ 3 H/FTED /_xl_ Coo_rER . .,pA,er VAZoE 'e, _, '.' _ _, T'r AD, ,& ,v' ?/cD., , D, I w" _s_ c, ,Ce o.oo/p -3oo uJwc _,, _, z_v _T -- _oMF'oS_'/'a otv tt Jl ._Oz.EC A _/cE F/_um_ '¢- 8':/ 268 o Ji.___ I I ! I -11 I I_ I J 0 PARTS LIST FOR POWER DRIVE CIRCUIT AND PRE-DRIVE STAGE R 1 - R 2 R 3 - R 4 R 9 - RI0 RII - RI2 RI3 - RI4 RI5 - RI6 RI7 - RI8 RI9 " R20 D1 -_ DI0 DII_DI4 D17 - DI8 D19 "D20 DZI - DZ2 DZ3 - DZ4 DZ5 = DZ6 wine 8.2K- I/2W Composition 22K - 1/2W 270.*. 10W 47.,L- 112W 130_- 10W 1.5K- IW C ompo s it ion Wire Wound Composition Wire Wound Compos Itlon 330Jr- I/2W Composition 60 .n.- 25W non inductive Wire Wound lN458A 379A (WX) INII86A 1Nl615 IN756 - 8-P- V IN3340B - /°° V IN3345 -- 14o V Tolerange *5% +5% ,5% --5% .5% .5% ±1% z .g _'2o /c_2_ Ol "* 04 2N657A Q5 - Q6 2NI050A Q7 - Q8 2N657A 09 - OlO STC 2501 FIGURE 4-q/ 270 PARTS LIST (Continued) T 1 (See Design IT- Table _- _ T 2 - T 3 Core - AM-1 (Arnold) 1 MEL Silectron Np NS1 NS2 NS3 - 100 turns #30 DFV wire - 50/50 turns (Bifilar) #30 DFV wire - 10 turns #20 DFV wire - 1 turn #10 DFV wire T 4 Core m Np - 52033 - IS (Magnetics) N S " 9 turns #12 DFV wire T 5 - T 6 Core- 80023- 1/8A Np - 84 turns No. 30 DFV wire N S - 42 turns No. 30 DFV wire T 7 Core 50002 - 1A Np - 420 turns No. Tapped at 210 turns N S - 324 turns No. Tapped at 162 turns 30 DFV wire 30 DFV wire FIGURE _ - _ 271 |I I I t I I ! I I _.° I q ,,o. } F.. c_ T_ Par.._tt RI R2 R3 R4 R5 R6 R7 R8 R9 "* Rll RI2 o R24 R13 RI4 R15 RI6 R17 RI8 - RI9 R20 R21 R22 R23 R24 SCRI DI - DI3 DA1 Cl C2 C3 C4 Q1 Q2 Q3 - Q6 Q7 Q8 PARTS LIST FOR OVERLOAD SENSE AND FEEDBACK CIRCUIT Value 33 I/2W 4o7K 1W 470_- 2W 5.6K 1/2W 2K - 1/2W 3.9- 1W IK- 1/2w Co mpos ition Composition Co mpo s ition Composition C ompos ition Composition Co mp os itlon 5K- lW Potentiorneter 2 00.n.- 2W 1.5K - 1/2W 2.2K- 1W 29K- 1/2W XK- X/:,W 1 00._- 1/2W 22K - 1/2W 4.7K- IW 120.,_.- 5W 1.SK- 1/2W 240J_- 2W 1K- 1/2W 2K- 1W Compos ition Composition Composition Co mpos ition Composition Co mpos ition Co topos ition Composition Wire- Wound Composition Composition Co mpos ition Co rnpo s ition 241 WA- WM 1N458A 4E2OM-8 0.1 _fd - 200 WVDC • 05 axfd - 200 WVDC 47 _fd - 35 WVDC . 05 ttfd - 200 WVDC STC 1739 2N1486 2N657A 2N491 2N657A Tolerance -,,s% *5% *5'/o *570 *5% *57o +570 -,-lO% +17o ±570 *57° -,-570 ..-57o +570 +5% .570 *5% *5% +5% +5% Westinghouse 20V e4V -1o7. .lo7. 4"1070 ii0% FIGURE 4 --_ 273 Part T1 - T3 T4- T6 T7 T8 T9 PARTS LIST FOR OVERLOAD SENSE AND FEEDBACK CIRCUIT (Continued i Value 50061 - ID Np - 1 turn N S - 1868 turns 50000- IA Np - 876 turns N S - 132 turns Tapped at 66 turn 80524 1/4A (MA) Np - 120 turns N S - 50 turns Nrese t- 124 turna 31Z394 31Z294 Tolerance No. 30 DFV No. 40 DFV No. 36 DFV No. 30 DFV No. 30 DFV No. 40 DFV Sprague Sprague FIGURE 4 - c_ Z74 ql Q_ 9 v /0 % "z TE_M/N,_C /0 _IFFECEnTIAI. /TmPI/F/E £ /-EEL)BA c_ C/_CUl'7" F',Gu_ e "I" - 9+ Z75 Par___! }%1 R2 R3 1%4 R5 R6 R7 QI Q2 Q3 Q4 DZI DZ2 PARTS LIST FOR DIFFERENTIAL AMPLIER FEEDBACK CIRCUIT Value 15K 3oo./x- 1 5K 300/1- 3K 900 400 Tolerance metal film i1% metal film *1% metal rum *1% metal film el% metal film el % metal film el% metal film el% 2NI132 2NI 132 2N657A 2N657A (matched for VBE characteristic) IN938B 1N3026B FIGURE _- 9S" 276 ! ]Part No, R1 R2 R3 R4 R5 R6 R7 R8 R9 RI0 =R17 RII =RI6 R12 -RI4 R13 R15 R18 RI9 R20 R21 R22 R23 R24 R25 D1 D2 - D4 c1 C2 C3 C4 QI Q2 Q3 - Q6 Q9- QI2 Q7 - Q8 PARTS LIST FOR 200 WATT VOLTAGE REGULATOR Value Tolerance 270-,I/2W 470,, IW 510._. 10W 2o2K 1/2W 5.6K 1/2W 47K I/2W 680_tl/2W I.SK I/2W 3.3K l/2W 10K I/2W 2.2K I/2W 2.2K 1/2W 4.7K I/2W 39K 1/2W 3.3K I/2W 3K l/2W IK W.W. 47K I/2W 1 OK 1/2W 2K l/2W I.8K I/2W I.IK 5W Composition e5% Composition e5% Wire Wound *5% Composition e5% Compos itlon *5% Composition e5% Composition ±5% metal film i1'% metal film el % Compos ition e5% Co mpos itlon e5 % Composition ±5% Co mpo sition e5 % Compos itlon e5% Composition e5% metal film ..1% potentiometer Composition ..5% Compos ition ..5% Composition ..5% Compos ition +5% Wire Wound ..1=5% 1 N3892 I N458A 100Add + 200 WVDC 1000 ;_£d + 35 WVDC .027 Add + 400 WVDC • 015 Add _ 400 WVDC --lO% ..20% • 10_/, ..10% Matched palr 2N3194 With matched Ide, Vbe, R=at. (can use one 2N2528 i STC 5204 2N697 2N697 2NII32A FIGURE _ - c_"7 278 PARTS LIST FOR 200 WATT VOLTAGE REGULATOR. (Continuod) Part No. L1 L2 DZ1 DZ2 DZ3 Value Tolerance IMH- 10Acap I0.2 MI-I_ - 10A cap 1N2823B - _o V i5% 1N3021B - i | _/ ±5% 1NTS:A _ _.IV .s% F:GURE "_-9 7 279 0 0 0 0 0 0 O, u 0 0 0 | 4) 4) X h- U C_ 4) r'--- .• .. ............. i............ I I i i i [ ! { -i.......i.... .......... L ......... 0 f_ r,l L._, _ i i ,I i ,, ,,, i , , i-'i' i ] L F,I i, i i J i i i ii i in I I ! _z ......... _ J . . I o o i J o o_ g " " " 2"80 .... \I -'. - ll Hl 281 il!lll vlllL o I'\ IP L}Lc=E Dr=LA_" PuLse_eN6.P.ATOR_ L,_{ _wo_ (,o,c) l J I(+"_) C1_N I__ATO_. _oC>ULA'rlM6 _VAVE. A M PLIN e, t ¼ _"l'A N_" P_L_. AMpu'ru_ _z- M OOOLA1"oIe. L t ,_1_ pLIFIEER. :.. 'Ebb ,' C_ ÷ E1 J • F--__ +. 0 I o _"_ u _'z: ")- I O0 z8z u_ G \ , j u m 0 Q k k 0 \ a0 283 t"q o o o tt_ o =_ -2 I o 0 0 o 4J u ID \i . MoDJLA//,V_W _WEEP _VE \ .\ J I 1 x L % iUII II \ 1 j, _oNT_oL _LU_ _UMM ED _/AVE5 -[I 1 i! _ LsE rH F_ Z3 L /1/_rFL//_A_.SAmPz./we E/ euRE I1 o_-,_o, k/o,..'r.,,,c.,C% Logo FI_UFIF.. 4 - I 03 285 .... ......... t k - _r ...................... l ! @ s,i ® U o ___--_ Z U_ o,1 I_, I_ _" ,1_ _ _t4 _ n:l ,.o t_ o 0 ! u o o N o ! 286 G wee_oWA_. I n i _OTAT/_ S#CTZ/AL _JTI_JT F/c- ul_ _- I o 5" Z87 I'111! i I ilIJU: !, _n i , , i , , , , a 0', 0 \ , p a_TTd_y oAT_o_T 289 0 0 0 u_ 0 U o.H_:; N 0 U 0 o- _ e- • o 0 • _ _ 1%1 0 0t W d ¢1 _u Z J o_o z U.. d) t_ 7 O_ I I _m_ ........... I_ . I I _, __I r_ L_ k_ _ 0 Z t_ } C) _u • " ° i ° I /- @ N f3- ;f c5 .Z I Parts List - PWM Static Inverter Power Stage Item Type Quantity Power Transistors Reverse Current Block Diodes Zener Diodes Balancing Reactors Divider Resistors Base Drive Resistors Reactive Current Diodes TA2110 IN3918 IN3350- 220V- 50W See Figure 4-I I 3 50K 10W ±5% Wire Wound l.$A -,lOW' __5_oWire Wound IN3918 180 18 360 90 180 180 6 FIGURE 4-- [I 0 292 t-, I I I iI i | I; I ! ! I i t / / I \ \ I t- k U o /1: I Q 4o If 0(1. o k t- i-t / E Y 2-- I w o ± at t. Cl t./ I- It u_ 1: t----- _ r-------- _ L._ , _ r------- 0 ..j 1- 1I: _ j _. ,r UJ _ _ u2 11; ul ,C I-- Z I- 00 O Rd Rd V --X---- 4 --k- _aM=aa_ _v2- k_ I I. RM= Maximum Transistor Leakage Resistance _. Rm _L4inimum Transistor Leakage ResiStance 3. a is Ratio of RM to Rm 4. Rd is Voltage Divider Resistor • 0 ......... • i I 1.1 1.2 1.3 1. Divider Resistor- Va_ue Vs t 7/1,I64 :-I_-'K - Figure 4 - 112 Voltage Unbalance Factor - k 1.5 1. q 1.7 1.8 1.9 294 z. 0 k&a a=20 2.1 '2.2 2.3 2.4 t _::)AI..A NC i N ¢_ _--_AC:TO DESIGN / ..... ,illi .8_.o" ---'- f o i_mq I._N io m. I I I ii 1,4:1: COI2__.' i 9 LAM_NA'F__is .o_4",',._-(qyMu 8_ C OI L<_ "_IP- I I'1_ _- _lt°l_J i i li II I "J I F,Co_l_ "t"- I I =-9 295 l l I / I / I / i/ I\ , l I- \ I U \ o .3 / i i ° ! \ \ \ 0 l I I I I I l I I I I I I i [ E I [ [ t t I ,r fiJ + 0 | /--- h- 0 -J M Z I- 7 ° _::::::::_ h- i t- J 0 W. u3 < o > I I_,l _ N 2. q_ y_ r_ C_ ! E3 ---t( c_j Ln uJ Q_ _D _J £., ,I IIJ :I: II II I.I) I! I 13 E E F J t_= :3 ,= "1 .. I . i la ,41 L I ( I ' : I IIi Parts List - DC-DC Converter = Q4A = Q4B Q1 = Q2 Q3A = Q3B US = Q6 SCR 1 = SCR 2 D 1 =D 2 D 3 D 4 D 5 = D 6 = D 7 = D 8 D 9 = D10 = Dll = Dl2 D13 = D14 D15 a = DI5 b D16 = D17 Di8 = D21 C 1 = C 2 C 3 C 4 = C 5 C 6 = C 7 C 8 L 1 L 2 L 3 R 1, R 2 R 3 = DI9 = D20 FIGURE 4-1 I "'F 299 STC 2105 STC 2501 2N1486 C80D (selected for high DV/DT) 1N3009B - 130V - 10W IN4045 INl184 IN3009B- I30V- 10W IN1190 (or fast recovery equivalent) IN3041B- 75 V - lW 1N2913 (50W) 15 V- 50W 1N3189 4E 20-8 16tA-f - 100 WVDC 24tA f - 100 WVDC 0.75/_f - 375 WVDC 0.5tAf - 400 WVDC 24t.lf - 100 WVDC 8 micro hy. - class H 32 micro hy. 50 micro hy. 100/L- 10W ±5% 9.1K - 5W _5% - class H - class H Wire Wound Wire Wound R4, R 5, R R , R14' 15 16' R17 R 6, R 7 R 8, R 9, R 0, Rll,l R12, R13 R18 R19 R20, R23 R24 R25, R26 R27, R28 R21, R22, R29, R30 T _ Drive Transformer (Class H} T 2 Power Output Transformer (Class H) T 3 = T4 Timing Core (Class H) T 5 - Drive Transformer (Class H} T 6 - Drive Transformer (ClassH) T 7- Drive Transformer (Class H) MA- 1 Magamp (Class H) NP = 21T-CT NS = 6T-CT NP = 12T-CT NS = 39T-CT NP = NS = 2T 100fL- 1 W ±5% 2 • 34fL-25W ±5% • 195.,_- 25W 4-570 150K - 10W ±5% 5.9;l-250W +5% 50J_.pot - 1W ±5% 15/L- lW 4-570 5K pot - lW *5% 3.3 K -1W ±5% I0/I- IW _5% 100/l-i W ±5% 2 -#7 wire -. 162" x . 410" -128" x . 410" -#I0 wire -. 128" x 410" NP = 1275T NS = 59T - CT -#38 wire -#30 wire NP = 50T-CT #18 wire NSI= 5T-CT #16 wire NS2= 5T-CT #12 wire NS3=50T-CT #28 wire NP=250T-CT #34 wire NS=45T-CT #26 wire Gate - 1350 T #30 wire Bias - 1300T #33 wire Control - 4000T #40 wire Compos ition Wire WOund Wire Wound Wire Wound Wire Wound Wire Wound Compos ftfon Wire Wound Compos ition Composition Gompo s ition Rect. Wire Rect. Wire Rect. Wire FIGURE 4- 117 300 +2.4 i Q49 D29, D30, D 31 D32 RI0 3' RI0 8' RII3 RI04, RI09' Rl14 RI05' RII0' RII5 RI0 6, RII I' RII 6 RI0 7' RII2' Rll 7 R 118 2N2218 IN756 - 8.2V = .4W IN751 = 5.1V = .4W 27K- lW ±5% 2 10K - 1 W ±5% 2 1OK = 1 W ,-570 2 47K - 1 W .+5°70 2 I0K - I W -,-570 2 4.7 K - 1 W ±5% 2 All resistors are composition. 314 FIGURE 4- IB D _.,,.,..- __._¢_ "q- 13_ 316 Parts List - Driver Stages Q50' Q51' Q56' Q57' Q62' Q63 Q54, Q5_ Q60' Q61, Q66, Q67 Q52, Q53, Q58, Q59' Q64' Q65 D33, D34' D37, D38, D41, D42 D35, D36, D39, D40, D43, D44 Rll 9' R129, RI39 R160, R162, R164 R120' RI30' R140 R161' R163, R165 RIE1, R1E 3, R131, RI32, R141, R 142 R122' R124, RI25, R128, RI33, R134, R135, R R143, R144, R147, RI48 RI26, R 127' R136' R 137' R145' R146 2N2218 2N1937 2N1723 1N3875 138' 1N3915 150.l--lW ±5% Composition 1K - 1 W ±5% Composition 2 180A.-1 W ±5% Composition 2 10A-1 W 4-5% Composition 2 10A-10W 4-5% Wire Wound 1/t-10W 4-5% Wire Wound 100v%-10W 4-5% Wire Wound Driver Transformers (45 required) - TA -(Class H) FIGURE 4-! _4 317 VT, To DC-Oc- 0 kIEOT_AL F, Gu R e. "4.- ras" 318 Parts List - Voltage Regulator Sense Circuit D5 2--)_D5 7 VT I, VT 2, R158 R159 C40 VT 3 IN659 (Class H} Voltage Transformer s a = _'/_I 180 - 1 W _-5% 2 I K pot.-I W 15% C ompo s it ion Wire Wound 4.7L_-fd / 10 WVDC _c._ I 2 , I(c .f. Sc_ \ T vo 3zo (i 0 t__ ........ -I it, i,_ i _ ,-...it._,_. iI " _'..]._ !, .. I_ / 321 k..__ oI I ; . c,2_;Z:,5--r :I_ . _!U i ! I --< de-:.Z'o. 0 322 _rrw_ 323 IV .20 I II "-'--_ --" I C 324 STARTING AND STEADY STATE WAVEFORMS McMURRAY-BEDFORD INVERTER RESISTIVE LOAD (WITH TUNED FILTER) @ ® | l , s i .... : _- _._ o , l _.,.--, .,._ ',_*,' i ,.1 _t' I l t 1 ; I "4.. Y" "-,' ' I _il_lJl_f_J_lli_l_ n ] I I _ • ,, i , , -- , I I I i ( I I l I ® ® @ © ® 'L__/L-_I I ! x_ ! ,f--... W i I ' ,,, ? • i i I I _.. _ i, _ I I I I I. ) ' _ : ) I ) , l ® ® 325 FIGURE _--,_"-- I # McMUII_AY-BEDFORD INVERTER WAVE FORMS INDUCTIVE LOADING ,_o :I I ! i,.llai,_r' _ I , * . lllili,_.*i -- i .i-lr I ;I ." '1 I II a i I #i _ ! lJ I __._D....---f-:'' ' " ' I I II i i i + + ,+-+-+++u, +, , ,_+++•, :#_+I,', ,,,, ' . .; . . : o, @ ® © @ @ ,#161l-r: _r, qlrlr,_i, il .4,#al_._,.il. Blia lm.,.I L_ L_ t_ ® (2) @ _Z6 FIGURE 4-1-l_ i "_dm_'m"_" _ ,,q f C ,C,e. "_ --._- 1"3 327 ,_PL sd'P V'o_.TA_r ._ ® _ _ I 1/ \ t mm m m 328 t--_- --I- !rl_ r--_ _ o i u_ ÷ !.o | J:l ! k: 2_ u2 t[ 330 + + l ..... + I Z ; _.. +i. " t ...... I- .... t : : I • i l : : , : , , • • : i -!:-= 24_.... .... + : .-ii '|/ l;! _---:...... i i i ' -I!-2. t ;.... : i _ ! _ ! ! ! I ' .... ; .... --_ ....... : .... ; .... + .... •t To&_..,I,1-,+._o_,+t+,_.o++_,t+ ........ __I.___.Z_+A. _2 _ l '.__+ _.L [ _ .... T + , + ¢j Ib ....... 331 L_ 332 i i t i L I ! 333 334 !_ • 4 ¸ _ i. ........ _ |_ t---r-- b i __ ....i • ! t_, ,! f L i - - i i : . A . :ila, -:-._-_.. iI -- --_n--- i m , I I --_- i _ i t . .... i ,! , i' I !2-1 ! t .... .... ? i i .... ......... L 335 i336 - i -._ i i • ,! ii. i::i ::: --- ... ::: :: 'i" : :: ::12 _ht & tw!e, t. t. • i:.i :i i , • i-- 1 I I i ! 11.: : ! I ! ! ': i "- :i ::i !., 121 222: L_ d_ i '-:? i! I: 337 338 339 i-i li¸ _ 340 341 a) o ;4 o 4.1 III °f4 lJ 0 u i/.l: 0 <_._ 0 k 0 ,t-I t_ e_ < Q k 0 U g. II I,¢ u_ II • u • !1 "_ II " "r, " "_ " "_ . ell_ _)m el_ e_ I.o ,,0 i/1 I N r,- "0 II ,'-¢ 0 u ®,-1 _N ! 4) _ _ .d 342 " " i,-I T_ ,,# rq rJ 0 .!:1 4..I ill o r_ t_ ,-4 ;.i H A i.n 14j o 0 k u,-4 oe4 o • e0 IB U 0 t4 0 ,60 u 14 o _4 e'4 o" N oN q if °-'¢ N mOO tO 0 • • • IXO''4 _0 _ _ Jl 8 eul_ I10 0-'4 • 14,,...4 14 s_IA_ siO'T zoS:)s_puI ,zo:)TL.-.TSOT,ze_ TVSOI. 343 N U O O tD o4a 4._ q-4 o o 4.a u o _u°f-I k ns o uS c4 q) ,.4 • -.4 w._ ,,o nl a) o_ 0 o 0 QO 4) 0 0 4_ u '0 4) 4-) k_ 4.b k 0 '_ -.I • II • I| • |1 ,..4 H Q Q • m I_ Q g 0 r._ o r./) • _ o r/) o o_ e_ e_ o_ I I o e-4 eeqauI _TqnD e_nnTOA. _zol_npuz .zelTT_ 0eT_o_ 344 t_ o o. -6-) 4) o. 0 4_ k_ I-i 0_ 0 r_ m 0 1,0 4_ 41 U m 4,4, • " i ,,0 Q • o _o 8Rgn g 0 og gDlt _t ? ..... . o o i,,._ II m k ,-a o,-1 _N I ' I I ' I t I ! r,.1 u 0 f] f,,a .,11,,I, ,n-4 o ltDd) S,,a P,0 aP .,,o,,ll 0r_ f_ k U o lq U a) 0 .d o q-4 4_ rj Q < ® c_ :> o 4-1 u t_ 1"4 4-1 ' '' i c3 (,4 p--t I ' 3, ' oi ' ,=1 ' ol o 346 ! I u o o ee.e o 4.b b_ f., 0 ¢: g m; I -,q rj o rJ d d_ ,,-4 ,'18 4...4 •-q [.,4; • • o _o H_IU e_e6 ommo <;<'4;<; : m ,q Q qD 0 u <; P,4 4,a o Jo ,,0 m 6 ,,,,I | 0 O I! 4_ i',- ! :> | ut_r_._.. - ,oo,-i _ro:lIT,.,l ":D "V T_;O.T. oJ _o ! ,,D ,_ (%1 348 o @ o 6 @ 4J < 4.a 0 ,V4 4_ 0 4._ _e k d qO 4_ ,ll.,4 4) q-I B-4 0 o:.: J ! 0 0 4,a -,4 ,a \ \ ,_ I ' I _ 347 t o u N O -_ N II o u clS 0 = o. ID 1:1 4.1 0 o k 0 o u m e _,+ oN ,,e.d N = I1 0 _o u _J N t + I I ,,,o i @ 1:1 4J 0 tN 0 ÷ .4- u_ _ _ I I I 350 0U I ! 0 s k "dn • k 0 u_ _ o _ U U k 0 0 0 N I _0 N 0 _0 _P [.., ! k 0 4_ U 351 NN N °tO ! 0 q) u k _) 352 N0 N 0 U 0 353 0 o u I o k u u o o ,..1 k 0 II II II II U U U U o _ _ _. :, ,._ u 1! II) N I ' I ' ' I ' I ' I 0 0 0 0 0 0 F_ I bO _3 r_ 0 oO 0 °_ 0 o 354 -.4 ! be p,4 ÷ ÷ N ÷ ! | uoT_,_['n_ _ _'e:;io A _,nc_n 0 _ug:).x_cI 355 0 _o ! un I _x @ 13o co 'I,=4 "_==t I ' I t i (M I _o °*.4 o ¢) 4-) t_ 0 u lU t-- I- 2 U.._ Q, ,,.t I- o - I ul o ! I ! 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Inverter-converter parallel operation

Abstract

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Inverter-converter parallel operation

Abstract

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