A four-bit parallel processor LSI array was designed and fabricated using COS/MOS integrated-circuit technology. The design features include the provision for interconnecting groups of parallel-processor chips to form an expanded processor of any desired word length. This 800-transistor "computer on a chip' circuit has the logic capability of a medium-size, medium-speed, general-purpose computer suitable for sophisticated scientific data processing. The ability to fabricate this device repetitively was demonstrated
Recognition and representation of parallel processable streams in computer program
The goal of our research is to decrease the execution time of scientific computing applications. We ...
As part of our research on very high performance parallel architectures, we have been investigating;...
A high speed parallel array data processing architecture fashioned under a computational envelope ap...
In a computer having a large number of single-instruction multiple data (SIMD) processors, each of t...
Goodyear Aerospace delivered the Massively Parallel Processor (MPP) to NASA/Goddard in May 1983, ove...
The architecture and VLSI design of a new massively parallel processing array chip are described. Th...
The present state of electronic technology is such that factors affecting computation speed have alm...
Two ways to exploit chips with a very large number of transistors are multicore processors and progr...
Highly parallel computing architectures are the only means to achieve the computation rates demanded...
Scientific applications are increasingly being implemented on massively parallel supercomputers. Man...
AbstractUK based picoChip Design's new PC101 is a huge parallel device integrating 430 16-bit proces...
High performance systolic arrays of serial-parallel multiplier elements may be rapidly constructed f...
With the present availability of parallel processors of vastly different architectures, there is a n...
The current capabilities of LSI techniques for speed and reliability, plus the possibilities of asse...
Recognition and representation of parallel processable streams in computer program
The goal of our research is to decrease the execution time of scientific computing applications. We ...
As part of our research on very high performance parallel architectures, we have been investigating;...
A high speed parallel array data processing architecture fashioned under a computational envelope ap...
In a computer having a large number of single-instruction multiple data (SIMD) processors, each of t...
Goodyear Aerospace delivered the Massively Parallel Processor (MPP) to NASA/Goddard in May 1983, ove...
The architecture and VLSI design of a new massively parallel processing array chip are described. Th...
The present state of electronic technology is such that factors affecting computation speed have alm...
Two ways to exploit chips with a very large number of transistors are multicore processors and progr...
Highly parallel computing architectures are the only means to achieve the computation rates demanded...
Scientific applications are increasingly being implemented on massively parallel supercomputers. Man...
AbstractUK based picoChip Design's new PC101 is a huge parallel device integrating 430 16-bit proces...
High performance systolic arrays of serial-parallel multiplier elements may be rapidly constructed f...
With the present availability of parallel processors of vastly different architectures, there is a n...
The current capabilities of LSI techniques for speed and reliability, plus the possibilities of asse...
Recognition and representation of parallel processable streams in computer program
The goal of our research is to decrease the execution time of scientific computing applications. We ...
As part of our research on very high performance parallel architectures, we have been investigating;...