Add to ORKGThe important features of the multiport (double entry) automatic placement and routing programs for standard cells are described. Measured performance and predicted performance were compared for seven CMOS/SOS array types and hybrids designed with the high speed CMOS/SOS cell family. The CMOS/SOS standard cell data sheets are listed and described
Major silicon-gate CMOS/SOS processes are described. Sapphire substrate preparation is also discusse...
The complete sequence used to manufacture complementary metal oxide semiconductor (CMOS) integrated ...
Metal oxide semiconductor and GaAs devices are discussed. Digital and analog circuits are described....
A low cost, quick turnaround technique for generating custom metal oxide semiconductor arrays using ...
The NASA/MSFC high speed CMOS/SOS standard cell family, designed to be compatible with the PR2D (Pla...
The CMOS/SOS design rules prepared by the RCA Solid State Technology Center (SSTC) are described. Th...
Design and performance of logic circuit chip for computerized design of MOS integrated circuit array
The cell placement techniques developed for use with the standard transistor array were incorporated...
The entire complement of standard cells and components, except for the set-reset flip-flop, was comp...
The design of a MOS 256-bit Random Access Memory (RAM) is discussed. Technological achievements comp...
A family of standardized thick-oxide P-MOS building blocks (standard cells) is described. The inform...
High performance systolic arrays of serial-parallel multiplier elements may be rapidly constructed f...
Two silicon CMOS application specific integrated circuits (ASICs), a data generation chip, and a dat...
This thesis addresses the circuit and layout issues of the Complementary Metal-Oxide-Semiconductor (...
Digital subsystem design and development employing n-channel and p-channel in MOS FET units in compl...
Major silicon-gate CMOS/SOS processes are described. Sapphire substrate preparation is also discusse...
The complete sequence used to manufacture complementary metal oxide semiconductor (CMOS) integrated ...
Metal oxide semiconductor and GaAs devices are discussed. Digital and analog circuits are described....
A low cost, quick turnaround technique for generating custom metal oxide semiconductor arrays using ...
The NASA/MSFC high speed CMOS/SOS standard cell family, designed to be compatible with the PR2D (Pla...
The CMOS/SOS design rules prepared by the RCA Solid State Technology Center (SSTC) are described. Th...
Design and performance of logic circuit chip for computerized design of MOS integrated circuit array
The cell placement techniques developed for use with the standard transistor array were incorporated...
The entire complement of standard cells and components, except for the set-reset flip-flop, was comp...
The design of a MOS 256-bit Random Access Memory (RAM) is discussed. Technological achievements comp...
A family of standardized thick-oxide P-MOS building blocks (standard cells) is described. The inform...
High performance systolic arrays of serial-parallel multiplier elements may be rapidly constructed f...
Two silicon CMOS application specific integrated circuits (ASICs), a data generation chip, and a dat...
This thesis addresses the circuit and layout issues of the Complementary Metal-Oxide-Semiconductor (...
Digital subsystem design and development employing n-channel and p-channel in MOS FET units in compl...
Major silicon-gate CMOS/SOS processes are described. Sapphire substrate preparation is also discusse...
The complete sequence used to manufacture complementary metal oxide semiconductor (CMOS) integrated ...
Metal oxide semiconductor and GaAs devices are discussed. Digital and analog circuits are described....